FBK Irst Trento

Trento, Italy

FBK Irst Trento

Trento, Italy
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Vasilache D.,FBK Irst Trento | Vasilache D.,IMT Bucharest | Boldeiu G.,IMT Bucharest | Moagar V.,IMT Bucharest | Tibeica C.,IMT Bucharest
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2010

The aim of this paper is to present two different types of MEMS switch structures developed in IMT: bridge and cantilever. For these two configurations were chosen different length of bridges and cantilevers; also, for the actuation pads used were considered different size. Finite Element Method simulations were performed in order to determine the pull-in voltage. Comparison between simulated and measured results will be presented for the bridge type switch structure. © 2010 SPIE.


Vasilache D.,FBK Irst Trento | Vasilache D.,IMT Bucharest | Constantinidis G.,FORTH IESL MRG Heraklion | Dragoman M.,IMT Bucharest | And 8 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2010

The aim of this work was to develop a new MEMS switch structure for millimeter wave applications, which can be integrated with other more complex devices for developing of reconfigurable filters or antennae for microwave or millimeter wave frequency range. Electrostatic force was chosen for the switching operation, which seams to be the only way to obtain high reliable and wafer scale manufacturing techniques at these frequencies. Different geometries of the switching element were designed and manufactured in order to study the mechanical stability of these structures; the measured actuation voltage, of about 24,5V, shows an acceptable value for the further applications. Measured and simulated results of these structures (insertion losses of about 0.75dB@60GHz and isolation >50dB@60GHz) were in good agreement and are promising for further applications in this frequency range. © 2010 SPIE.


Vasilache D.,FBK irst Trento | Colpo S.,FBK irst Trento | Margesin B.,FBK irst Trento | Giacomozzi F.,FBK irst Trento | And 2 more authors.
UPB Scientific Bulletin, Series C: Electrical Engineering | Year: 2012

This paper presents a new method of tapered walls through silicon wafers via holes (TSV) manufacturing, using a variable isotropy DRIE (Deep Reactive Ion Etching) process type. TSV manufacturing method is presented (based on Bosch type anisotropic etching), as well as process optimization for a very good control over the wall angles.


Savadkoohi P.T.,FBK irst Trento | Margesin B.,FBK irst Trento | Vasilache D.,FBK irst Trento | Giacomozzi F.,FBK irst Trento
Proceedings of the International Semiconductor Conference, CAS | Year: 2010

In the last years MEMS Switches and related MEM components have encountered a great interest in the technology community for their outstanding intrinsic characteristics. MEMS Switches in particular offer low insertion loss, higher isolation, almost zero power consumption, small size and weight at very low inter-modulation distortion, which makes them suitable for many applications. The MEMS technology has demonstrated also to be able to provide potentially high quality components for other passive RF and microwave devices such as capacitors and inductors. In this paper we extend our research activities on MEM technology to the design of tuneable capacitors based with in-plane movement. © 2010 IEEE.


Vasilache D.,FBK irst Trento | Colpo S.,FBK irst Trento | Ronchin S.,FBK irst Trento | Giacomozzi F.,FBK irst Trento | Margesin B.,FBK irst Trento
Proceedings of the International Semiconductor Conference, CAS | Year: 2010

A new process for through-wafer interconnects was studied by our group. This new process was developed to facilitate metallised through wafer via holes manufacturing. V-shape profile can contribute to an easier metallisation process and better adhesion. Manufacturing process use the possibility to change the isotropy in the Deep Reactive Ion Etching (DRIE) equipments from anisotropic to completely isotropic. Two slightly different processes were used in order optimize the technology and to see the changes introduced by isotropic/anisotropic processes sequence. © 2010 IEEE.


Vasilache D.,FBK irst Trento | Colpo S.,FBK irst Trento | Giacomozzi F.,FBK irst Trento | Margesin B.,FBK irst Trento | Chiste M.,FBK irst Trento
Proceedings of the International Semiconductor Conference, CAS | Year: 2011

A new method for conductive via's using gold electroplating is presented. Tapered walls through wafer via (TWV) holes were made using a variable isotropy DRIE process, with a very good control over the obtained angles angles of 11.3 and 21.8 were obtained with errors smaller than 10%. Barrier and seed layers were deposited in via's performed by PVD (Physical Vapor Deposition) techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via's. © 2011 IEEE.


Avancini A.,FBK irst Trento | Ceccato M.,FBK irst Trento
Proceedings - 11th IEEE International Working Conference on Source Code Analysis and Manipulation, SCAM 2011 | Year: 2011

More and more web applications suffer the presence of cross-site scripting vulnerabilities that could be exploited by attackers to access sensitive information (such as credentials or credit card numbers). Hence proper tests are required to assess the security of web applications. In this paper, we resort to a search based approach for security testing web applications. We take advantage of static analysis to detect candidate cross-site scripting vulnerabilities. Input values that expose these vulnerabilities are searched by a genetic algorithm and, to help the genetic algorithm escape local optima, symbolic constraints are collected at run-time and passed to a solver. Search results represent test cases to be used by software developers to understand and fix security problems. We implemented this approach in a prototype and evaluated it on real world PHP code. © 2011 IEEE.


Vasilache D.,FBK irst Trento | Chiste M.,FBK irst Trento | Colpo S.,FBK irst Trento | Giacomozzi F.,FBK irst Trento | Margesin B.,FBK irst Trento
Proceedings of the International Semiconductor Conference, CAS | Year: 2012

This paper presents for the first time influence of the silicon resistivity over the DRIE processes. Our aim was to develop a new process for tapered walls through silicon vias (TSVs) with a good control over the walls angle. Different wafer types were used and a dependency of resistivity was found, with an important impact over the TSVs shape. Solution found is presented and experiments performed to obtained designed TSVs. © 2012 IEEE.

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