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Dragoi V.,EV Group | Cakmak E.,EV Group Inc. | Pabo E.,EV Group Inc.
Romanian Journal of Information Science and Technology | Year: 2010

Metal -lms can be used as bonding layers at wafer-level in MEMS manufacturing processes for device assembly as well as just for elec- trical integration of di®erent components. One has to distinguish between two categories of processes: metal thermo-compression bonding on one side, and bonding with formation of an eutectic alloy layer or an intermetallic compound. The di®erent process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with special emphasis on vacuum packaging) metal wafer bonding is a very important technology in MEMS manufacturing processes.


Dragoi V.,EV Group | Pabo E.,EV Group Inc. | Burggraf J.,EV Group | Mittendorfer G.,EV Group
Microsystem Technologies | Year: 2012

Wafer bonding became during past decade an important technology for MEMS manufacturing and waferlevel 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples. © Springer-Verlag 2012.


Dragoi V.,EV Group | Pabo E.,EV Group Inc.
ECS Transactions | Year: 2010

Wafer bonding processes offer valuable solutions not only for MEMS devices but more recently for wafer-level 3D interconnects, advanced packaging and LED applications. The increased complexity of the wafer bonding based applications requires very accurate process design. Unfortunately bonding process selection and design is not always well documented or understood and some important details may not be considered, possibly resulting in major issues during product prototyping or even manufacturing. The main topics to be considered for wafer bonding process selection are summarized and explained. ©The Electrochemical Society.


Flotgen C.,EV Group | Pawlak M.,EV Group | Pabo E.,EV Group Inc. | Van De Wiel H.J.,Integrated Materials | And 2 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2013

The impact of process parameters on final bonding layer quality was investigated for Transient Liquid Phase (TLP) wafer-level bonding based on the Cu-Sn system. Subjects of this investigation were bonding temperature profile, bonding time and contact pressure as well as the choice of metal deposition method and the ratio of deposited metal layer thicknesses. Typical failure modes in Inter-Metallic Compound (IMC) growth for the mentioned process and design parameters were identified and subjected to qualitative and quantitative analysis. The possibilities to avoid abovementioned failures are indicated based on experimental results. © 2013 SPIE.


Cakmak E.,EV Group Inc. | Dragoi V.,EV Group | Capsuto E.,STR | McEwen C.,STR | Pabo E.,EV Group Inc.
Microsystem Technologies | Year: 2010

Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates. The main advantages of using this approach are: low temperature processing (maximum temperatures lower than 400°C), surface planarization and tolerance to particles contamination (the intermediate layer can incorporate particles with the diameter in the layer thickness range). The main bonding layers properties required by a large field of applications/designs can be summarized as: isotropic dielectric constants, good thermal stability, low Young's modulus, and good adhesion to different substrates. This paper reports on wafer-to-wafer adhesive bonding using SINRTM polymer materials. Substrate coating process as well as wafer bonding process parameters optimization was studied. Statistical analysis methods were used to show repeatability and reliability of coating processes. Features of as low as 15 μm size were successfully resolved by photolithography and bonded. An unique megasonic-enhanced development process of the patterned film using low cost solvent was established and proven to exceed standard development method performance. © 2009 Springer-Verlag.


Flotgen C.,EV Group | Corn K.,EV Group Inc. | Pawlak M.,EV Group | Van De Wiel Hj.,Integrated Materials | And 2 more authors.
ECS Transactions | Year: 2012

Cu-Sn Transient Liquid Phase (TLP) wafer-level bonding is an interesting solution for wafer-to-wafer stacking technologies, due to its compatibility with 3D interconnections as well as vacuum sealing applications. The work presented here is analysing typical Cu-Sn TLP wafer bonding issues as occurrence of voids, bonded wafers pair bow and incomplete layer transformation with respect to process parameters as maximum bonding temperature, bonding time and contact (bonding) pressure. © The Electrochemical Society.


Dragoi V.,EV Group | Pabo E.,EV Group Inc.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2015

Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding proceb and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding procebes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glab frit bonding and metal-based bonding. The outgabing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgabing. Additionally the selected bonding proceb must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each proceb for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for proceb characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addrebed will be introduced with examples. © COPYRIGHT 2015 SPIE.


Pabo E.F.,EV Group Inc. | Pabo E.F.,EV Group
2010 12th Electronics Packaging Technology Conference, EPTC 2010 | Year: 2010

Wafer to wafer bonding was an enabling technology for MEMS because it provided the needed protection for the devices by capping them at the wafer level allowing them to survive in the required operating environments such as the automotive environment. The two earliest bonding processes used for this wafer level capping were anodic and glass frit bonding. Due to the constant pressures for cost reduction, size reduction, performance increase, increased integration, and shortened product life cycles the integration of MEMS devices with CMOS based circuitry is increasingly being considered and implemented. Consequentially, bonding, whether wafer to wafer or chip to wafer, has the additional role of being an enabling technology for the integration of CMOS and MEMS device. In this technology, the bond joint typically has multiple roles such as providing mechanical strength, electrical signal conductance, and sealing against various environmental agents or for vacuum encapsulation. ©2010 IEEE.


Greener J.,University of Toronto | Li W.,University of Toronto | Ren J.,University of Toronto | Voicu D.,University of Toronto | And 3 more authors.
Lab on a Chip - Miniaturisation for Chemistry and Biology | Year: 2010

We report a cost-efficient and easy to implement process for fabricating microfluidic reactors in thermoplastic materials. The method includes (i) the fabrication of an imprint template (master), which consists of a photoresist deposited on a metal plate; (ii) the thermoembossing of the reactor features into polymer sheets; (iii) the activation of the embossed and planar thermoplastic surfaces; and (iv) the low-temperature bonding of these surfaces. The generality of the method is established by fabricating microfluidic reactors with a complex geometry in a range of thermoplastic polymers, including cycloolefin, polycarbonate, and UV-transparent acrylic polymers and by the multiple, high-fidelity use of the master. © 2010 The Royal Society of Chemistry.


Patent
EV Group Inc. | Date: 2012-11-21

The present invention relates to an accommodating device for accommodation and mounting of a wafer for application of a fluid to a top of the wafer with the following features: a revolving ring section with: d) a revolving upper edge, e) a revolving recess and f) a circumferential wall running from the upper edge to the recess, a contact plane (A) arranged within the ring section for the accommodation of the wafer on a contact surface of the wafer, wherein the ring section by means of accommodation of the wafer forms with said wafer an accommodating space for accommodation of the fluid.

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