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Flotgen C.,EV Group | Corn K.,EV Group Inc. | Pawlak M.,EV Group | Van De Wiel Hj.,Integrated Materials | And 2 more authors.
ECS Transactions | Year: 2012

Cu-Sn Transient Liquid Phase (TLP) wafer-level bonding is an interesting solution for wafer-to-wafer stacking technologies, due to its compatibility with 3D interconnections as well as vacuum sealing applications. The work presented here is analysing typical Cu-Sn TLP wafer bonding issues as occurrence of voids, bonded wafers pair bow and incomplete layer transformation with respect to process parameters as maximum bonding temperature, bonding time and contact (bonding) pressure. © The Electrochemical Society. Source


Dragoi V.,EV Group | Pabo E.,EV Group Inc.
ECS Transactions | Year: 2010

Wafer bonding processes offer valuable solutions not only for MEMS devices but more recently for wafer-level 3D interconnects, advanced packaging and LED applications. The increased complexity of the wafer bonding based applications requires very accurate process design. Unfortunately bonding process selection and design is not always well documented or understood and some important details may not be considered, possibly resulting in major issues during product prototyping or even manufacturing. The main topics to be considered for wafer bonding process selection are summarized and explained. ©The Electrochemical Society. Source


Flotgen C.,EV Group | Pawlak M.,EV Group | Pabo E.,EV Group Inc. | Van De Wiel H.J.,Integrated Materials | And 2 more authors.
Microsystem Technologies | Year: 2014

Wafer-level Cu-Sn intermetallic bonding is an interesting process for advanced applications in the area of MEMS and 3D interconnects. The existence of two intermetallic phases for Cu-Sn system makes the wafer bonding process challenging. The impact of process parameters on final bonding layer quality have been investigated for transient liquid phase wafer-level bonding based on the Cu-Sn system. Subjects of this investigation were bonding temperature profile, bonding time and contact pressure as well as the choice of metal deposition method and the ratio of deposited metal layer thicknesses. Typical failure modes in intermetallic compound growth for the mentioned process and design parameters have been identified and were subjected to qualitative and quantitative analysis. The possibilities to avoid abovementioned failures are indicated based on experimental results. © 2013 Springer-Verlag Berlin Heidelberg. Source


Dragoi V.,EV Group | Pabo E.,EV Group Inc. | Burggraf J.,EV Group | Mittendorfer G.,EV Group
Microsystem Technologies | Year: 2012

Wafer bonding became during past decade an important technology for MEMS manufacturing and waferlevel 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples. © Springer-Verlag 2012. Source


Dragoi V.,EV Group | Pabo E.,EV Group Inc.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2015

Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding proceb and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding procebes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glab frit bonding and metal-based bonding. The outgabing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgabing. Additionally the selected bonding proceb must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each proceb for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for proceb characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addrebed will be introduced with examples. © COPYRIGHT 2015 SPIE. Source

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