Zarandy A.,Hungarian Academy of Sciences |
Rekeczky C.,Eutecus Inc.
International Journal of Circuit Theory and Applications | Year: 2011
Topographic and non-topographic image processing architectures and chips, developed within the CNN community recently, are analyzed and compared. It is achieved on a way that the 2D operators are collected to classes according to their implementation methods on the different architectures, and the main implementation parameters of the different operator classes are compared. Based on the results, an efficient architecture selection methodology is formalized. © 2010 John Wiley & Sons, Ltd. Source
Agency: Department of Defense | Branch: Navy | Program: SBIR | Phase: Phase I | Award Amount: 80.00K | Year: 2011
Eutecus proposes to design and develop the next generation of advanced sensor electronics to improve existing UAV based persistent surveillance and sense-and-avoid capabilities. The new device will consist of the following main components: (i) a specific sensor-processor front-end sensitive in VIS/NIR wavelength with minimum array size of 1024x1024 and frame rates above 1kHz; and (ii) a generic, scalable multi-core processor back-end with embedded algorithms supporting real-time image stabilization and multi-fovea feature/signature analysis for improved terrain/object recognition and sense-and-avoid type processing. The ROIC carrier of the advanced sensor component will be implemented in ASIC, while the multi-core processor solution in high-end FPGA. The integrated product will meet defense-grade requirements. Proof-of-concept hardware development is planned in Phase I combined with field tests in order to validate the technology and provide input for refining Phase II goals. Eutecus is working with multiple Prime contractors (including NGC, LMCO and BAE all provided support letters) to ensure that design objectives of this program will be optimized for relevant defense applications.
Agency: Department of Defense | Branch: Missile Defense Agency | Program: SBIR | Phase: Phase II | Award Amount: 1.50M | Year: 2008
Eutecus proposes to develop scalable focal-plane sensor-processor array chips, 3D integrated with various sensors (e.g. InGaAs) sensitive in different IR spectral domains (e.g. NIR-SWIR). As opposed to the integrating type approaches, the sensor interface (read-out integrated circuit, ROIC) of the proposed design will contain precise resistive trans-impedance amplifiers (RTIAs) and fast analog-to-digital (AD) converters tightly coupled to a digital processor array, which will allow very high temporal sampling rates combined with near sensor algorithmic calculations. The proposed device will be able to handle input frequencies up to the megahertz (MHz) range. The processors will be equipped with local data memory per pixel, a multiple-add type arithmetic unit, a special statistical unit, and a morphological unit. The proposed sensor-processor chip will be able to perform Fourier analysis or calculate other computationally intensive linear (e.g. mean, convolution), non-linear (e.g. min, max, median) or binary (mathematical morphology) operations, and provide the processed output at a speed of few thousand frames per second. The output can be either an image and/or a decision, being able to trigger instantaneously the main processor of the host system when a certain object / target or a special visual event (identified through its space-time-spectral signature) occurs.
Agency: Department of Defense | Branch: Missile Defense Agency | Program: SBIR | Phase: Phase I | Award Amount: 100.00K | Year: 2006
We propose to develop novel space-time signature extraction algorithms and an associated reconfigurable multi-modal computational platform. In Phase I we will integrate a high-performance standalone vision system (Bi-i, EUTECUS) and a multi-spectral fusion system (Fu-P, IMAGIZE) built from state-of-the-art commercial and military components. This system will have a multi-spectral multi-target tracking and discrimination (MS-MTTD) capability handling multiple sensory inputs. Since the first Bi-i and Fu-P prototypes are already available there is a chance for rapid MS-MTTD prototyping by directly interfacing the two systems and synchronizing the associated software layers and algorithmic modules. It is expected that this prototype MS-MTTD system will enable enhanced warhead/decoy tracking and discrimination under difficult imaging conditions. The system will be able to perform low latency real-time analysis of large number of simultaneous potential targets based on static as well as kinematic and multi-spectral chromatic and thermal properties. This system will serve as the basis for subsequent Phase II development of a compact, ultra high-speed MS-MTTD platform which will enable the integration into various kill vehicles.
Agency: Department of Defense | Branch: Navy | Program: STTR | Phase: Phase II | Award Amount: 499.77K | Year: 2005
This STTR Phase II proposal is based on work completed under the STTR Phase I grant entitled "Focal Plane array processors with adaptive visual range and millimeter wave sensors" (Contract No. N00014-04-M-0212). In this Phase II project, we propose the development of two lines of ultra-high speed focal plane sensor and processor arrays equipped with (i) adaptive image sensors sensitive in the visual, NIR range, and (ii) uncooled nanoantenna MOM detector array sensitive in the far IR/THz domain respectively. The extraordinary computational performance of the digital CNN processor array will enable the capturing and processing of up to 10,000 frames per second in real-time in many image processing tasks. The sensor-processor chips will be integrated into a standalone vision system (demonstrator) and the capabilities of the new devices will be demonstrated via a high-speed multiple target tracking algorithm.