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Rekeczky C.,Eutecus Inc. | Kozek T.,Imagize LLC
2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010 | Year: 2010

A novel real-time signal processing device has been designed and implemented for improved target feature extraction, discrimination, and tracking. The device utilizes a unique combination of advanced signal processing techniques for multi-spectral fusion and image analysis. It incorporates state-of-the-art algorithm and the associated electronics to combine the functions of a multi-spectral fusion (MSF) engine and a multi-target tracking and discrimination (MTTD) engine. The resulting compact MSF-MTTD system, currently is capable of processing image flows from two external sensors (e.g. infrared and visible) by utilizing the processing power of massively parallel cellular nonlinear processor architectures at different levels of processing. Within this framework topographic data fusion (Stage 1) is followed by parallel feature extraction (Stage 2) and the analysis, tracking and discrimination (Stage 3) of multiple targets at ultra-high frame rates (>1000 fps). The compact (<2in3) light-weight (<25g), low-power (<5W for the entire system) prototype of the multi-core MSF-MTTD engine and system has been implemented on high-end FPGAs and will be described in this paper. © 2010 IEEE.


Zarandy A.,Hungarian Academy of Sciences | Zarandy A.,Pázmány Péter Catholic University | Rekeczky C.,Eutecus Inc. | Szolgay P.,Hungarian Academy of Sciences | And 2 more authors.
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2015

Cellular Neural/Nonlinear Networks (CNN) were invented in 1988, as an easy to implement, easy to program computer architecture for image and signal processing. This initiated intensive international research activities that lead to both theoretical (e.g. universality, stability studies in array dynamics) and experimental results (e.g. cellular sensor-processor chips and cellular algorithms). This overview paper summarizes the history of the CNN research and overviews the current activities in this field. Other areas are also discussed which were fostered by the results of the 25 years of CNN research: memristor architectures and processing, spin-torque oscillator architectures, many-core FPGA processing and industrial vision chips. © 2015 IEEE.


Rodriguez-Vazquez A.,University of Seville | Rodriguez-Vazquez A.,Anafocus | Carmona R.,University of Seville | Dominguez Matas C.,Anafocus | And 7 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2010

This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information and hence high processing speed. The top layer includes an array of optical sensors which are parallel-connected to the second layer, consisting of an array of mixed-signal read-out and pre-processing cells. Multiplexing is employed so that each mixedsignal cell handles several optical sensors. The two remaining layer are respectively a memory (used to store different multi-scale images obtained at the mixed-signal layer) and an array of digital processors. A prototype of this architecture has been implemented in a FDSOI CMOS-3D technology with Through-Silicon-Vias of 5μm x 5μm pitch. © 2010 Copyright SPIE - The International Society for Optical Engineering.


Szabo V.,Pázmány Péter Catholic University | Rekeczky C.,Eutecus Inc.
2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010 | Year: 2010

The goal of this paper is to introduce a new tracking framework, which exploits dynamic feature and signature selection techniques for data association models. It performs robust multiple object tracking in a noisy, cluttered environment with closely spaced targets. This method extends the back-end processing capabilities of tracking systems by creating a hierarchy between the parallelly extracted features. These features are dynamically selected based on spatio-temporal consistency weight function, which maximizes the robustness of data association, and reduces the overall complexity of the algorithm. © 2010 IEEE.


Zarandy A.,MTA SZTAKI | Fekete D.,MTA SZTAKI | Foldesy P.,MTA SZTAKI | Soos G.,MTA SZTAKI | Rekeczky C.,Eutecus Inc.
2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010 | Year: 2010

Displacement calculation algorithm is implemented on a heterogeneous sensor processor architecture, constructed of a mixed signal medium resolution processor array, and a digital, low resolution, foveal processor array. The algorithm is designed as an initial step of an airborne navigation framework. It features multi-scale multi-fovea processing. © 2010 IEEE.


Zarandy A.,Hungarian Academy of Sciences | Rekeczky C.,Eutecus Inc.
International Journal of Circuit Theory and Applications | Year: 2011

Topographic and non-topographic image processing architectures and chips, developed within the CNN community recently, are analyzed and compared. It is achieved on a way that the 2D operators are collected to classes according to their implementation methods on the different architectures, and the main implementation parameters of the different operator classes are compared. Based on the results, an efficient architecture selection methodology is formalized. © 2010 John Wiley & Sons, Ltd.


Grant
Agency: Department of Defense | Branch: Navy | Program: SBIR | Phase: Phase I | Award Amount: 80.00K | Year: 2011

Eutecus proposes to design and develop the next generation of advanced sensor electronics to improve existing UAV based persistent surveillance and sense-and-avoid capabilities. The new device will consist of the following main components: (i) a specific sensor-processor front-end sensitive in VIS/NIR wavelength with minimum array size of 1024x1024 and frame rates above 1kHz; and (ii) a generic, scalable multi-core processor back-end with embedded algorithms supporting real-time image stabilization and multi-fovea feature/signature analysis for improved terrain/object recognition and sense-and-avoid type processing. The ROIC carrier of the advanced sensor component will be implemented in ASIC, while the multi-core processor solution in high-end FPGA. The integrated product will meet defense-grade requirements. Proof-of-concept hardware development is planned in Phase I combined with field tests in order to validate the technology and provide input for refining Phase II goals. Eutecus is working with multiple Prime contractors (including NGC, LMCO and BAE all provided support letters) to ensure that design objectives of this program will be optimized for relevant defense applications.


Grant
Agency: Department of Defense | Branch: Missile Defense Agency | Program: SBIR | Phase: Phase II | Award Amount: 1.00M | Year: 2012

The main goal of the proposed program is to develop and integrate a laser ranger processor/engine based on Eutecus'XENON line of massively parallel, cellular many-core processors (TRL 5) with a recently prototyped multi-channel fusion-tracking processor/engine (TRL 6). The implementation will be completed in defense-grade rad-tolerant/rad-hard field programmable gate array (FPGA) technology also improving the robustness of space-time and spectral domain signature analysis and tracking performance. Eutecus will work closely with leading FPGA Vendors (Xilinx, Inc., Altera Co.) and several Defense Prime Contractors (LMSSC, Raytheon and Northrop) to meet MDA requirements for several key program elements (primarily ABMD and ABIR) of the Ballistic Missile Defense System (BMDS). Eutecus proposes to design and develop the next generation of two key elements of future interceptor seekers: (i) a range imager front-end sensitive in the 800-1400 nanometer wavelength (NIR/SWIR) operating at frame rates above 10kHz; and (ii) a three-channel, scalable multi-core processor back-end with embedded fusion-tracking algorithms supporting real-time multi-spectral (SWIR-MWIR-LWIR) feature/signature analysis and calculations required for range imaging and fusion-tracking at ultra-high speeds (typically in the 1-10 kHz range). Prototype hardware will be developed in Phase II combined with field tests in order to validate the technology for Phase III transition.


Grant
Agency: Department of Defense | Branch: Navy | Program: SBIR | Phase: Phase II | Award Amount: 749.99K | Year: 2012

Eutecus proposes to design and develop the next generation of advanced sensor electronics to improve existing UAV based persistent surveillance and sense-and-avoid capabilities. The new device will consist of the following main components: (i) a specific sensor-processor front-end sensitive in VIS/NIR/SWIR wavelength with minimum array size of 1024x1024 and frame rates above 1kHz; and (ii) a generic, scalable multi-core processor back-end with embedded algorithms supporting real-time image stabilization, range estimation and multi-fovea feature/signature analysis for improved terrain/object recognition and sense-and-avoid type processing. The ROIC carrier of the advanced sensor component will be implemented in ASIC, while the multi-core processor solution in high-end FPGA. The integrated product will meet defense-grade requirements. Prototype hardware development is planned in Phase II combined with field/flight tests in order to validate the technology and provide input for technology transition/insertion. Eutecus is working with multiple DoD Prime Vendors to ensure that design objectives of this program will be optimized for relevant defense applications.


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