Gielen G.,ESAT MICAS |
Dobbelaere W.,ON Semiconductor |
Vanhooren R.,ON Semiconductor |
Coyette A.,ESAT MICAS |
Esen B.,ESAT MICAS
Proceedings - International Test Conference | Year: 2014
Electronics are increasingly being embedded in a growing number of applications in our daily life. This demands strong reliability and robustness of those electronic systems. The IC manufacturing process not being perfect, however, inevitably results in some fabricated parts having defects. Test methods must detect such faulty ICs before shipment. While the fault coverage of testing for digital integrated circuits in industry today already reaches the sub-ppm level, this is not yet the case for analog integrated circuits or the analog part in mixed-signal ICs. This invited talk will review some techniques that are being explored in industrial practice to aim for sub-ppm-level coverage for the analog and mixed-signal circuits as well. This will be illustrated with some practical examples from automotive IC designs. © 2014 IEEE.
Tytgat M.,ESAT MICAS |
Steyaert M.,ESAT MICAS |
Reynaert P.,ESAT MICAS
Journal of Infrared, Millimeter, and Terahertz Waves | Year: 2012
The design and measurements of a 200 GHz downconverter in 90 nm standard CMOS are presented. A positive conversion gain of +6.6 dB, a noise figure of 29.9 dB and an output bandwidth of 3 GHz are measured for an LO power of -14.9 dBm. The conversion gain remains within 3 dB for an RF frequency between 186 and 212 GHz. Downconversion of BPSK and QPSK signals is demonstrated with eye diagrams and constellation plots with data rates over 4 Gbit/s. A mathematical analysis is made of the MOSFETs in the triode region and a new small-signal parameter κ is introduced, which enables the design of the mixing transistors for minimum conversion loss. © Springer Science+Business Media, LLC 2012.
Moons B.,ESAT MICAS |
De Brabandere B.,ESAT VISICS |
Van Gool L.,ESAT VISICS |
Verhelst M.,ESAT MICAS
2016 IEEE Winter Conference on Applications of Computer Vision, WACV 2016 | Year: 2016
Recently convolutional neural networks (ConvNets) have come up as state-of-the-art classification and detection algorithms, achieving near-human performance in visual detection. However, ConvNet algorithms are typically very computation and memory intensive. In order to be able to embed ConvNet-based classification into wearable platforms and embedded systems such as smartphones or ubiquitous electronics for the internet-of-things, their energy consumption should be reduced drastically. This paper proposes methods based on approximate computing to reduce energy consumption in state-of-the-art ConvNet accelerators. By combining techniques both at the system- and circuit level, we can gain energy in the systems arithmetic: up to 30 X without losing classification accuracy and more than 100 X at 99% classification accuracy, compared to the commonly used 16-bit fixed point number format. © 2016 IEEE.
Francois B.,ESAT MICAS |
Reynaert P.,ESAT MICAS |
Wiesbauer A.,Infineon Technologies |
Singer P.,Infineon Technologies
European Microwave Week 2010, EuMW2010: Connecting the World, Conference Proceedings - European Microwave Conference, EuMC 2010 | Year: 2010
A switching mode RF power amplifier that employs a narrowband filter directly connected to the output, is presented. The efficiency improvement compared to a conventional class B PA and the influence of a transmission line between the PA and this filter is investigated. These techniques are illustrated by circuit simulation and verified by measurements. It is shown how the transmission line between the filter and the PA will influence both the efficiency and the distortion of the PA. © 2010 EuMA.
Gielen G.,ESAT MICAS |
Maricau E.,ESAT MICAS |
De Wit P.,ESAT MICAS
Proceedings -Design, Automation and Test in Europe, DATE | Year: 2011
The paper discusses reliability threats and opportunities for analog circuit design in high-k sub-32 nanometer technologies. Compared to older SiO2 or SiON based technologies, transistor reliability is found to be worse in high-k nodes due to larger oxide electric fields, the severely aggravated PBTI effect and increased time-dependent variability. Conventional reliability margins, based on accelerated stress measurements on individual transistors, are no longer sufficient nor adequate for analog circuit design. As a means to find more accurate, circuit-dependent reliability margins, advanced degradation effect models are reviewed and an efficient method for stochastic circuit reliability simulation is discussed. Also, an example 6-bit 32nm current-steering digital-to-analog converter is studied. Experiments demonstrate how the proposed simulation tool, combined with novel design techniques, can provide an up to 89% better area-power product of the analog part of the circuit under study, while still guaranteeing a 99.7% yield over a lifetime of 5 years. © 2011 EDAA.
Cornelissens K.,Catholic University of Leuven |
Steyaert M.,ESAT MICAS
Analog Circuit Design - Robust Design, Sigma Delta Converters, RFID | Year: 2011
In comparator-based switched-capacitor circuits, OTAs are replaced by comparators and current sources. Instead of an OTA forcing a virtual ground condition, a comparator steers current sources until it detects a virtual ground. Different possibilities to use this principle in a ΔΣ A/D converter are evaluated. A pseudo-differential implementation with preset minimizes the requirements for the comparator and the current source. Due to the operation of the circuit, feed-back noise-shaping filters with half delay integrators are preferable. An implementation of a comparator-based switched-capacitor ΔΣ A/D converter in a 1 V, 90 nm CMOS technology demonstrates the feasibility. © 2011 Springer Science+Business Media B.V.
Sarafianos A.,ESAT MICAS |
Pichler J.,Infineon Technologies |
Sandner C.,Infineon Technologies |
Steyaert M.,ESAT MICAS
2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings | Year: 2015
This paper presents a fully integrated capacitive DC-DC converter with a wide input voltage range. The folding Dickson converter is used to implement four discrete voltage conversion ratios, capable of operating over a wide input voltage range. A subconverter is added, enabling four additional voltage conversion ratios, improving the input voltage resolution from Vout to 1/2 Vout. This way, the extra conversion ratios increase the overall efficiency, and at the same time reduce output ripple specifications. Implementing this additional converter at the end of the Dickson cascade reduces the complexity of driving the extra power train switches. This improved folding Dickson converter achieves an average efficiency above 70% at maximum output power, and operates over an input voltage range of 2.5-8V for an output voltage of 1.2V. The converter has been implemented and validated in a standard 90nm technology. © 2015 IEEE.
Van Breussegem T.,ESAT MICAS |
Steyaert M.,ESAT MICAS
2010 IEEE 12th Workshop on Control and Modeling for Power Electronics, COMPEL 2010 | Year: 2010
This paper presents a fully integrated capacitive DC/DC-converter with a gearbox type topology. By merging multiple topologies the output voltage range is increased. The dual loop digital control improves load regulation compared with a conventional hysteretic control and reduces ripple under low load operation. The converter was implemented in a 90nm CMOS technology and measurements are presented.
De Smedt V.,ESAT MICAS |
Gielen G.,ESAT MICAS |
Dehaene W.,ESAT MICAS
Analog Integrated Circuits and Signal Processing | Year: 2014
This article presents a comparative study of a time-based sensor interface implemented in two standard CMOS technologies, 130 and 40 nm. The interface uses a ring oscillator to generate a pulse-width modulated signal of which the duty cycle is proportional to the sensor value. This results in a highly temperature- and supply voltage-independent output signal. Simulation results of both implementations are compared in terms of temperature and voltage dependence, power consumption and linearity. Also the noise propagation from the oscillator to the PWM output is discussed. Afterwards, the simulation results are compared to measured values of a 40-nm CMOS implementation. It is concluded that the interface topology is a robust solution for deep-submicron wireless sensor nodes in dynamic environments. © 2014, Springer Science+Business Media New York.
Stefanou A.,ESAT MICAS |
Gielen G.,ESAT MICAS
Electronics Letters | Year: 2011
Presented is a scheme for regenerative comparators to suppress the induced input-dependent sampling distortion and also to alleviate the impact of substrate noise coupled to the comparator. The proposed scheme is based on the concept of source degeneration and is realised by incorporating a resistor at the source terminal of the sampling transistors. The scheme is evaluated with transient simulations, by characterising the output waveform jitter of the comparator with eye diagrams, and it is proven effective in the presence of high input signals and substrate noise. © 2011 The Institution of Engineering and Technology.