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Lee S.,Georgia Institute of Technology | Baldwin D.F.,Engent Inc.
43rd International Symposium on Microelectronics 2010, IMAPS 2010 | Year: 2010

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications because it has narrowed the feasible assembly process window for achieving robust interconnect yield. In spite of such challenges, a high yield, nearly void-free assembly process has been achieved in the past research using commercial no-flow underfill material with a high I/O, fine pitch FCIP. The initial void area (approximately 7%) could cause early failures such solders fatigue cracking or solder bridging in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of underfill void nucleation in the no flow assembly process. Based on the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of voidfree assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively. This paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high yield, void-free assembly process leveraging a void formation model based on classical bubble nucleation theory. Indeed, the theoretical models were in good agreement with experimental results. Copyright© (2010) by IMAPS - International Microelectronics & Packaging Society. Source


Li Z.,Auburn University | Lee S.,Georgia Institute of Technology | Lewis B.J.,Engent Inc. | Houston P.N.,Engent Inc. | And 4 more authors.
Journal of Microelectronics and Electronic Packaging | Year: 2010

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material. Copyright © 2010 International Microelectronics and Packaging Society. Source


Li Z.,Auburn University | Lee S.,Georgia Institute of Technology | Lewis B.J.,Engent Inc. | Houston P.N.,Engent Inc. | And 4 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2010

Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing. © 2010 IEEE. Source


Li Z.,Auburn University | Lee S.,Georgia Institute of Technology | Lewis B.J.,Engent Inc. | Houston P.N.,Engent Inc. | And 4 more authors.
International Conference and Exhibition on Device Packaging 2010, Held in Conjunction with the Global Business Council, GBC 2010 Spring Conference | Year: 2010

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. No flow underfill is of a special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. This paper introduces the development of no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control and the underfill voiding analysis. Also different no flow underfill candidates are investigated for the best performed processing material. Copyright© (2010) by IMAPS. Source


Lewis B.J.,Engent Inc. | Baldwin D.F.,Engent Inc. | Houston P.N.,Engent Inc. | Smith B.,Charles Stark Draper Laboratory | And 4 more authors.
IMAPS International Conference and Exhibition on Device Packaging - In Conjunction with the Global Business Council, GBC 2011 Spring Conference | Year: 2011

IUHD offer order-of-magnitude increase in interconnect density for SOP. Small size leads to lower thermal resistance than COTS BGAs. Hybrid Si-encapsulant iUHD module offers better mechanical properties compared to all-Si and is thermo-mechanically stable with proper material selection: Stress driven mainly by encapsulant-Si ratio. Extremes in stress occur at 50% loading for standard material. Stress increases as CTE increases, even when accounting for effect of modulus. Source

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