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Li Z.,Auburn University | Lewis B.J.,Engent Inc. | Houston P.N.,Engent Inc. | Baldwin D.F.,Engent Inc. | And 3 more authors.
43rd International Symposium on Microelectronics 2010, IMAPS 2010 | Year: 2010

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies. Copyright© (2010) by IMAPS - International Microelectronics & Packaging Society.

Li Z.,Auburn University | Lee S.,Georgia Institute of Technology | Lewis B.J.,Engent Inc. | Houston P.N.,Engent Inc. | And 4 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2010

Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing. © 2010 IEEE.

Thirugnanasambandam S.,Auburn University | Zhang J.,Auburn University | Evans J.,Auburn University | Xie F.,Engent Inc. | And 5 more authors.
InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM | Year: 2012

In this experiment, the thermal performance of different dimensional lead free wafer level chip scale package on laminate assemblies with SAC 305 alloys (3% Ag, 0.5%Cu) were recorded, to determine their reliability based on optimal dimensions of ball grid array, pad size and package structures. The test chips were of 6 x 6, 8 x 8 and 12 x 12 ball grid array packages with perimeter solder balls on a 0.4 mm pitch. The WLCSP assembly was subjected to high temperature accelerated life test of 1250 thermal cycles with -40°C to +125°C on a 50-minute thermal profile. The test was subjected to JEDEC JESD22-A104-B standard high and low temperature test in a single and dual zone environmental chamber to assess the solder joint performance. Reliability of the test chips was determined from the ability of components and solder interconnects to withstand the thermal stresses induced by alternating high and low temperature extremes. The SAC alloy micro structures of the components were studied in a scanning electron microscope to determine the impact of the IMCs on the solder joints. The results showed that the 6 x 6 ball grid array packages had better thermal reliability and main crack initiation position was at top right corner of the solder joints near the chip side. © 2012 IEEE.

Li Z.,Auburn University | Lee S.,Georgia Institute of Technology | Lewis B.J.,Engent Inc. | Houston P.N.,Engent Inc. | And 4 more authors.
Journal of Microelectronics and Electronic Packaging | Year: 2010

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material. Copyright © 2010 International Microelectronics and Packaging Society.

Fennell B.,Georgia Institute of Technology | Lee S.,Georgia Institute of Technology | Baldwin D.F.,Engent Inc.
Microelectronics Reliability | Year: 2016

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented. © 2016 Elsevier Ltd.

Lee S.,Georgia Institute of Technology | Baldwin D.F.,Engent Inc.
43rd International Symposium on Microelectronics 2010, IMAPS 2010 | Year: 2010

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications because it has narrowed the feasible assembly process window for achieving robust interconnect yield. In spite of such challenges, a high yield, nearly void-free assembly process has been achieved in the past research using commercial no-flow underfill material with a high I/O, fine pitch FCIP. The initial void area (approximately 7%) could cause early failures such solders fatigue cracking or solder bridging in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of underfill void nucleation in the no flow assembly process. Based on the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of voidfree assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively. This paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high yield, void-free assembly process leveraging a void formation model based on classical bubble nucleation theory. Indeed, the theoretical models were in good agreement with experimental results. Copyright© (2010) by IMAPS - International Microelectronics & Packaging Society.

Bhattacharya S.K.,Engent Inc. | Lewis B.,Engent Inc. | Wu H.,Engent Inc. | Hodge K.,Engent Inc. | And 4 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2015

The ultimate goal of this study is to address and overcome the critical barriers for implementing a low cost high yield manufacturing process using thermal compression bonding of copper pillars to a high density organic substrate with the aid of a nonconductive paste. First, a conventional reflow bonding of the copper pillars to the organic and ceramic substrate was conducted and reliability after air-to-air thermal cycling was compared for baseline evaluation. The selected test vehicle for this step was a pressure sensor module where ASIC and MEMS chips were mounted on both sides of a 6-layer organic and a 6-layer ceramic substrate using a solder paste and an underfill material. Thermal cycling of the constructed functional module showed superior reliability for the ceramic substrate compared to the organic. In the second step, a design of experiments was conducted to optimize process conditions for thermal compression bonding of the copper pillars in ASIC chips to both ceramic and organic substrates using a nonconductive paste in lieu of an underfill. The assembled substrates were thermally cycled under similar conditions to evaluate thermal reliability performance and mechanical integrity of the bonding. Results show better performance for the ceramic substrate compared to the organic. The conditions for dispensing a nonconductive paste and thermal compression bonding using an automated machine have been optimized for further evaluation and scaling up to manufacturing where dispensing of the nonconductive paste, placement of chips, and thermal compression bonding can be achieved in-situ with a single assembly tool with reduced cycle time. The substrate for high throughput manufacturing is a 3-layer (dielectric) high density organic allowing direct landing of fine pitch copper pillar to the conductor traces without any landing pads. © 2015 IEEE.

Houston P.,Engent Inc. | Lewis B.,Engent Inc. | Pathammavong K.,Engent Inc. | Sparks T.,Engent Inc. | Baldwin D.F.,Engent Inc.
Advancing Microelectronics | Year: 2010

As Military electronics continue towards higher performance and smaller form factors, interest in 3D die level integration has moved to the forefront. While current 3D packaging solutions, involving a combination of high density circuit boards with stacked ICs using wire bond interconnect, can satisfy some of the performance and form factor requirements, 3D die level integration is proving to be the solution of choice for many mission critical, applications. The key features of 3D die level integration are very high levels of integration, very small form factor packages (often chip scale in size), very low profile packages, low weight packages, and improved digital and RF performance. This paper will briefly review 3D integration technologies, present implementation strategies for 3D die level integration packaging, and present examples of 3D die level integrated packaging solutions.

Lewis B.J.,Engent Inc. | Baldwin D.F.,Engent Inc. | Houston P.N.,Engent Inc. | Smith B.,Charles Stark Draper Laboratory | And 4 more authors.
IMAPS International Conference and Exhibition on Device Packaging - In Conjunction with the Global Business Council, GBC 2011 Spring Conference | Year: 2011

IUHD offer order-of-magnitude increase in interconnect density for SOP. Small size leads to lower thermal resistance than COTS BGAs. Hybrid Si-encapsulant iUHD module offers better mechanical properties compared to all-Si and is thermo-mechanically stable with proper material selection: Stress driven mainly by encapsulant-Si ratio. Extremes in stress occur at 50% loading for standard material. Stress increases as CTE increases, even when accounting for effect of modulus.

Lewis B.J.,Engent Inc. | Baldwin D.F.,Engent Inc. | Houston P.N.,Engent Inc. | Xie F.,Engent Inc. | La L.H.,Engent Inc.
Proceedings - Electronic Components and Technology Conference | Year: 2013

Commonly, during the process development cycle for new products, limitations exist on the materials that are available for the prototype work. Most SMT devices are readily available in different formats and solder alloys to satisfy most of the needs for passive components, however, many times, IC devices are limited to what is available from the fab or IC brokers. These limitations range from die only available with aluminum, wirebond ready I/O metallization, pad layouts in fine pitch perimeter patterns or that the silicon wafers are already sawn and presented as singulated die. For applications where advancement in performance or miniaturizationis needed, and the benefits of flip chip technology are attractive, it is not a trivial task to be able to use these die. In these cases, the process of adding solderable plating technologies to the I/O bond pads is very favorable. The technologies are currently run for wafer lever plating baths, but very little has been done to evaluate singulated chip plating. Work in plating Ni/Pd onto the ALCAP structure has been performed to evaluate the process and feasibility of processing groups of singulated die with aluminum bond pads. The work to be detailed in this paper will go through the chemistries used in the plating process onto an aluminum bond pad that makes it suitable for flip chip processes. Several bumping structures, such as solder bumping over this Ni/Pd plating stack up and plating over gold or copper stud bumps before adding solder bumps, are evaluated. A process for low cost bumping the singulated flip chips is also detailed. The data for shear testing of 10 variations of bumping structures, before and after 500 liquid thermal shock cycles, is detailed. Finally, a comprehensive study for assembly of solder bumped flip chips, with the various selective plating processes, will be detailed as well as a detailed analysis of the TC reliability of this assembly approach. It will be shown that selective Ni/Pd plating onto singulated, ALCAP bare die can allow, for these die that are typically wire bonded, to be used in a practical approach, solder flip chip process. It will also be shown that these processes provide reasonable reliability results when compared to a mainstream, wafer processed, solder bumped flip chip die. © 2013 IEEE.

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