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Endicott, NY, United States

Bale D.S.,Endicott Interconnect Technologies Inc.
Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment | Year: 2010

A semi-analytic approximation to the weighting potential within monolithic pixelated CdZnTe radiation detectors is presented. The approximation is based on solving the multi-dimensional Laplace equation that results upon replacing rectangular pixels with equal-area circular pixels. Further, we utilize the simplicity of the resulting approximate weighting potential to extend the well-known Hecht equation, describing charge induction in a parallel plate detector, to that approximating the multi-dimensional charge induction within a pixelated detector. These newly found expressions for the weighting potential and charge induction in a pixelated detector are compared throughout to full 3D electrostatic and monte carlo simulations using eVdsim (eV Microelectronics Device SIMulator). The semi-analytic expressions derived in this paper can be evaluated quickly, and can therefore be used to efficiently reduce the size and dimensionality of the parameter space on which a detailed 3D numerical analysis is needed for pixelated detector design in a wide range of applications. © 2010 Elsevier B.V. All rights reserved.


Bale D.S.,Endicott Interconnect Technologies Inc.
Journal of Applied Physics | Year: 2010

In this paper, homogenization theory based on a multiple scale perturbation of the charge-transport equation is used to derive a mathematical framework for modeling the cumulative effect of Te inclusions in radiation detectors based on semi-insulating cadmium zinc telluride (CdZnTe). The derived framework naturally incorporates a wide range of physical models that may posit either a reduced electron lifetime due to enhanced trapping at inclusions, or an altered carrier speed due to a distorted electric field at inclusions, or both. The new framework is applied to a simplified version of the geometric model introduced by Bolotnikov [Nucl. Instrum. Methods Phys. Res. A 571, 687 (2007)], and it is shown that this results in a closed-form approximation to the reduced electron trapping time that depends in a rather simple way on fundamental inclusion parameters such as their mean size and number density. It is also demonstrated that this effective trapping time compares well with previously published simulation data for the geometric model. Further, the electron mobility-lifetime product that results from the reduced carrier lifetime is easily incorporated into Monte Carlo device simulation. Examples of simulated induction maps and pulse-height spectra for pixelated detectors that contain inclusions of various mean sizes and number densities are presented. © 2010 American Institute of Physics.


Patent
Endicott Interconnect Technologies Inc. | Date: 2011-03-28

A substrate for use in a laminated chip carrier (LCC) and a system in package (SiP) device having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can include thermoset and thermoplastic resin.


Patent
Endicott Interconnect Technologies Inc. | Date: 2011-07-25

An organic substrate capable of providing effective heat transfer through its entire thickness by the use of parallel, linear common thermally conductive openings that extend through the substrate, the substrate having thin dielectric layers bonded together to form an integral substrate structure. The structure is adapted for assisting in providing cooling of high temperature electrical components on one side by effectively transferring heat from the components to a cooling structure positioned on an opposing side. Methods of making the substrate are also provided, as is an electrical assembly including the substrate, component and cooling structure.


Patent
Endicott Interconnect Technologies Inc. | Date: 2011-04-08

A method of forming a circuitized substrate for use in electronic packages. A substrate layer is provided that has a copper pad on a surface. A conductive seed layer and a photoresist layer are placed on the surface. The photoresist is developed and conductive material is placed within the developed features and a second conductive material placed on the first conductive material. The photoresist and conductive seed layer are removed to leave a micro-pillar array. The joining and lamination of two circuitized substrate layers utilizes the micro-pillar array for the electrical connection of the circuitized substrate layers.

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