Endicott Interconnect

Endicott, United States

Endicott Interconnect

Endicott, United States

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Lin D.-S.,Stanford University | Wodnicki R.,General Electric | Zhuang X.,Stanford University | Woychik C.,Tessera Technologies, Inc. | And 10 more authors.
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control | Year: 2013

A promising transducer architecture for largearea arrays employs 2-D capacitive micromachined ultrasound transducer (CMUT) devices with backside trench-frame pillar interconnects. Reconfigurable array (RA) application-specified integrated circuits (ASICs) can provide efficient interfacing between these high-element-count transducer arrays and standard ultrasound systems. Standard electronic assembly techniques such as flip-chip and ball grid array (BGA) attachment, along with organic laminate substrate carriers, can be leveraged to create large-area arrays composed of tiled modules of CMUT chips and interface ASICs. A large-scale, fully populated and integrated 2-D CMUT array with 32 by 192 elements was developed and demonstrates the feasibility of these techniques to yield future large-area arrays. This study demonstrates a flexible and reliable integration approach by successfully combining a simple under-bump metallization (UBM) process and a stacked CMUT/interposer/ASIC module architecture. The results show high shear strength of the UBM (26.5 g for 70-¿m balls), high interconnect yield, and excellent CMUT resonance uniformity (s = 0.02 MHz). A multi-row linear array was constructed using the new CMUT/interposer/ASIC process using acoustically active trench-frame CMUT devices and mechanical/ nonfunctional Si backside ASICs. Imaging results with the completed probe assembly demonstrate a functioning device based on the modular assembly architecture. © 1986-2012 IEEE.


Zhang R.,Auburn University | Zhang J.,Auburn University | Evans J.,Auburn University | Johnson W.,Auburn University | And 4 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2011

With the transition to lead-free, the electronics industry has widely adopted matte Sn for use component surface finishes. However, it is well know that plated Sn finishes can result in Sn whisker formation. After significant work by numerous researchers, the exact mechanism for Sn whisker growth is still unknown. While industry standard test have been developed, there are no acceleration factors to correlate the laboratory test results to field life. Furthermore, testing (JESD22A121) of components with industry accepted mitigation strategies has still shown whisker growth in excess of allowable standards (JESD201A). The addition of bismuth, to Sn plating reduces whisker growth length. Sn whisker growth, solder wetting, backward compatibility and reliability are discussed. © 2011 IEEE.


Thomenius K.,Massachusetts Institute of Technology | Wodnicki R.,General Electric | Cogan S.,General Electric | Fisher R.,General Electric | And 12 more authors.
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control | Year: 2014

Mosaic annular arrays (MAA) based on reconfigurable array (RA) transducer electronics assemblies are presented as a potential solution for future highly integrated ultrasonic transducer subsystems. Advantages of MAAs include excellent beam quality and depth of field resulting from superior elevational focus compared with 1-D electronically scanned arrays, as well as potentially reduced cost, size, and power consumption resulting from the use of a limited number of beamforming channels for processing a large number of subelements. Specific design tradeoffs for these highly integrated arrays are discussed in terms of array specifications for center frequency, element pitch, and electronic switch-on resistance. Large-area RAs essentially function as RC delay lines. Efficient architectures which take into account RC delay effects are presented. Architectures for integration of the transducer and electronics layers of large-area array implementations are reviewed. © 2014 IEEE.


McCoy B.O.,Mayo Medical School | Techentin R.,Mayo Medical School | Buhrow B.,Mayo Medical School | Buchs K.,Mayo Medical School | And 3 more authors.
DesignCon 2010 | Year: 2010

Variability analysis is important in successfully deploying multi-gigabit backplane printed wiring boards (PWBs) with growing numbers of high-speed SerDes links. We discuss the need for large sample sizes to obtain accurate variability estimates of SI metrics (eye height, phase skew, etc). Using a dataset of 11,961 S-parameters, we demonstrate statistical techniques to extract accurate estimates of PWB SI performance variations. We cite numerical examples illustrating how these variations may contribute to underestimated or overestimated design criteria, causing unnecessary design expense. Tabular summaries of performance variation and key findings of broad interest to the general SI community are highlighted.

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