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Li H.,University of California at Santa Barbara | Li H.,Emerging Memory Group | Liu W.,University of California at Santa Barbara | Cassell A.M.,NASA | And 2 more authors.
IEEE Transactions on Electron Devices

Due to the enormous challenges of fabricating long horizontally aligned carbon nanotube (HACNT) bundle interconnects, there exists little research on characterization of long HACNT interconnects. In this paper, taking advantage of our unique HACNT fabrication process outlined in the companion paper, the electrical and self-heating characterization of long HACNT bundles are reported. Negative temperature coefficients of resistance for both per unit length resistance and metal-CNT contact resistance are confirmed from measurements. This first report on the electrical and thermal characterization fills the wide gap between CNT interconnect modeling efforts and corresponding experimental efforts by providing many important extracted parameters that are critical in various modeling and analyses. © 1963-2012 IEEE. Source

Li H.,University of California at Santa Barbara | Li H.,Emerging Memory Group | Liu W.,University of California at Santa Barbara | Cassell A.M.,NASA | And 2 more authors.
IEEE Transactions on Electron Devices

Although horizontally-aligned carbon nanotube (HACNT) interconnects are the most common scenarios that have been modeled and analyzed in theoretical research, fabrication of HACNT test structures has remained an enigma until now. Through addressing several fabrication challenges, this paper reports a novel process that enables fabrication of high-density, long (over hundred microns), and thick (up to micrometer) HACNT interconnects. Furthermore, horizontal CNT-based 2-D Manhattan structure is demonstrated by properly designing the catalyst and flattening process. These structures are crucial for building angled interconnects and on-chip passive devices. In addition, to address the contact issue between metal and thick HACNT bundles, a multistep lithography combined with specifically designed metal deposition technique is performed to ensure full contact configuration. Using such a process, test structures with arrays of various sizes of HACNT bundle interconnects are fabricated. The process developed in this paper provides an important platform for future research and technology development of CNT-based interconnects and passive elements. © 1963-2012 IEEE. Source

Khatami Y.,University of California at Santa Barbara | Khatami Y.,Intelligent Group | Li H.,University of California at Santa Barbara | Li H.,Emerging Memory Group | And 2 more authors.
IEEE Transactions on Nanotechnology

The superb properties of graphene such as high mobility, broad spectral range of optical transparency, high mechanical flexibility, and impermeability to moisture have made it a promising material for transparent conductor (TC) applications. To optimize the properties of graphene-based TCs, an in-depth understanding of the properties of graphene layers on different materials is crucial. In this paper, the electrostatics and charge screening of Bernal-stacked few-layer graphene (FLG) on surface-passivated semiconductors (SC) are investigated. A self-consistent method is developed, which calculates the equilibrium characteristics of the Schottky barrier at the interface and the charge distribution arising from the impurities on FLG and charge transfer from the SC to FLG. The developed model is applied to FLG/Si structures, and the charge distribution and charge screening effects are investigated. It is shown that with proper selection of doping concentration, the barrier height of the FLG/Si structure under study can be reduced by more than 400 mV, which is crucial in improving the contact resistance between FLG and SC. The self-consistent method and the analysis provide a pathway toward high-performance design of FLG-based TCs. © 2013 IEEE. Source

Ramesh A.,Ohio State University | Park S.-Y.,Ohio State University | Park S.-Y.,Emerging Memory Group | Berger P.R.,Ohio State University
IEEE Transactions on Circuits and Systems I: Regular Papers

Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T-2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic 1 and 0 V as a logic 0. Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of 6× 10-5mW per cell and dynamic power dissipation of &1.8× 10-7mW/MHz per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level. © 2011 IEEE. Source

Li H.,University of California at Santa Barbara | Li H.,Emerging Memory Group | Russ C.C.,Intel Corporation | Liu W.,University of California at Santa Barbara | And 3 more authors.
IEEE Transactions on Electron Devices

A comprehensive study of electrostatic discharge (ESD) characterization of atomically thin graphene is reported. In a material comprising only a few atomic layers, the thermally destructive second breakdown transmission line pulsing (TLP) current (It2) reaches a remarkable 4 mA/μm for 100-ns TLP and ~8 mA/μm for 10-ns TLP or an equivalent current density of ~3 × 10 8 and 4.6 × 108 A/cm2, respectively. For ~5-nm thick (~15 layers) graphene film, It2 reaches 7.4 mA/μm for 100-ns pulse. The fact that failure occurs within the graphene and not at the contacts indicates that intrinsic breakdown properties of this new material can be appropriately characterized using short-pulse stressing. Moreover, unique gate biasing effects are observed that can be exploited for novel applications including robust ESD protection designs for advanced semiconductor products. This demonstration of graphene's outstanding robustness against high-current/ESD pulses also establishes its unique potential as transparent electrodes in a variety of applications. © 1963-2012 IEEE. Source

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