EMemory Technology Inc.

Hsinchu, Taiwan

EMemory Technology Inc.

Hsinchu, Taiwan
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Huang S.-C.,National Chiao Tung University | Chen K.-H.,National Chiao Tung University | Chen H.-M.,EMemory Technology Inc. | Ho M.-C.,EMemory Technology Inc. | Shen R.S.-J.,EMemory Technology Inc.
IEEE Circuits and Systems Magazine | Year: 2010

One-time program (OTP) memories are programmed for memory design without electrostatic discharge (ESD) stresses. However, in reality, ESD events are not selective and thus ESD currents can falsely program OTP memory cells. Many integrated circuit (IC) designers focus only on improving OTP memory control architectures to avoid memory being falsely programmed without mentioning the ESD-introduced memory errors. This article investigates a new ESD architecture and novel ESD avoiding circuits, aiming to solve ESD-introduced memory falsely programmed issues. It should be noted that this article focuses on ESD circuit designs to protect OTP memory instead of OTP control architectures. With such new ESD schemes, our prototype circuits have demonstrated that memory cells can indeed be programmed at IC program mode without ESD stresses. © 2006 IEEE.


Huang S.-C.,National Chiao Tung University | Chen K.-H.,National Chiao Tung University | Lin W.-Y.,eMemory Technology Inc. | Lee Z.-L.,eMemory Technology Inc. | And 5 more authors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Year: 2012

An additional high-voltage pad is generally applied for one-time-programming (OTP) memory product applications. This may increase the complexity of input/output (I/O) pad arrangement and the area penalty. In this paper, a novel approach of I/O circuit embedded with the power-switch function is proposed for multifunction integrations in one I/O pad. The capabilities of high-voltage programming, I/O signal handling, electrostatic discharge protection and latch-up prevention for this novel circuit are well examined from silicon verifications. © 2006 IEEE.


Chen L.-C.,National Tsing Hua University | Chen L.-C.,eMemory Technology Inc. | Yeh M.-S.,National Nano Device Laboratories | Lin Y.-R.,National Tsing Hua University | And 4 more authors.
AIP Advances | Year: 2017

We propose the concept of the electrical junction in a junctionless (JL) field-effect-transistor (FET) to illustrate the transfer characteristics of the JL FET. In this work, nanowire (NW) junctionless poly-Si thin-film transistors are used to demonstrate this conception of the electrical junction. Though the dopant and the dosage of the source, of the drain, and of the channel are exactly the same in the JL FET, the transfer characteristics of the JL FET is similar to these of the conventional inversion-mode FET rather than these of a resistor, which is because of the electrical junction at the boundary of the gate and the drain in the JL FET. The electrical junction helps us to understand the JL FET, and also to explain the superior transfer characteristic of the JL FET with the gated raised S/D (Gout structure) which reveals low drain-induced-barrier-lowering (DIBL) and low breakdown voltage of ion impact ionization. © 2017 Author(s).


Sun W.-T.,Ememory Technology Inc. | Liu C.-J.,Ememory Technology Inc. | Lo C.-Y.,Ememory Technology Inc. | Ting Y.-J.,Ememory Technology Inc. | And 9 more authors.
2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011 | Year: 2011

A simple and low cost logic based single poly Flash memory technology, NeoFlash®, with fast programming and high reliability is demonstrated in this paper. Programming with channel hot-hole-induced hot-electron injection and erasure with uniform channel Fowler-Nordheim tunneling are utilized to achieve fast programming, high endurance and good reliability characteristics. Owing to its simple cell structure and operation schemes, only 3 additional non-critical masks are needed, and the complexity of process integration and device tuning is much reduced. The SONOS based technology has been successfully embedded into 0.35μm ∼ 65nm CMOS logic process. Because of electrons stored in nitride layer of ONO film, no tail bit during endurance and retention test is observed. As a result, NeoFlash® is a promising embedded Flash technology for SoC applications. © 2011 IEEE.


Kuo C.-W.,EMemory Technology Inc. | Hsu C.-J.,EMemory Technology Inc. | Lo C.-Y.,EMemory Technology Inc. | Kuo J.-M.,EMemory Technology Inc. | And 3 more authors.
2013 5th IEEE International Memory Workshop, IMW 2013 | Year: 2013

In this paper, program/erase (P/E) cycling characteristics of the novel p-type SONOS NeoFlash® has been thoroughly discussed. The change of vertical location in the nitride and density distribution in energy span of the trapped charges after cycling has been observed. Different ONO thickness and process of nitride film results in different amount of cycling degradation. The contribution of interface traps and ONO trapped/residue-charges to P/E cycling degradation has been successfully distinguished. © 2013 IEEE.


Shen R.S.-J.,EMemory Technology Inc. | Wu M.-Y.,EMemory Technology Inc. | Chen H.-M.,EMemory Technology Inc. | Lu C.C.-H.,EMemory Technology Inc.
Digest of Technical Papers - Symposium on VLSI Technology | Year: 2014

Various product applications bring up with increasing demands of logic NVM IP in advanced technology nodes. Encryption, security, functionality, and identification setting become indispensable in communication and high-end consumer electronics. A non-volatile memory cell, using anti-fuse programming mechanism to achieve high density and excellent data storage lifetime, is proposed. The unique cell design and operation scheme realize low programming-inhibit leakage current, fast program speed, and robust data retention. The memory macro is successfully demonstrated for one-time and multi-time programming applications with its full compatibility to sub-28nm and FinFET processes. © 2014 IEEE.


Shen R.,EMemory Technology Inc. | Chen H.-M.,EMemory Technology Inc. | Wu M.-Y.,EMemory Technology Inc.
IEEE Joint Conference - International Conference on IC Design and Technology, ICICDT 2016 and Solid State Systems Symposium, 4S 2016 | Year: 2016

Logic NVM, with no manufacturing change and high security behavior, provides a simple approach for mobile communication, autotronics and IoT applications. Those increasing product demands bring up with fast logic NVM IP advancement in advanced technology nodes. A logic NVM cell, using anti-fuse programming mechanism to achieve high density and excellent data storage lifetime, is presented in this paper. The cell design and operation scheme realize low programming-inhibit leakage current, fast program speed, and robust data retention in FinFET process. The memory macro is successfully demonstrated for one-time and multi-time programming applications with full compatibility to sub-16nm FinFET processes. © 2016 IEEE.


Chang W.-C.,EMemory Technology Inc. | Wu P.-C.,EMemory Technology Inc. | Po C.-H.,EMemory Technology Inc. | Lin C.-F.,EMemory Technology Inc. | And 2 more authors.
IEEE Joint Conference - International Conference on IC Design and Technology, ICICDT 2016 and Solid State Systems Symposium, 4S 2016 | Year: 2016

An electrically programmable and erasable memory macro with low power and low voltage operation is implemented for the applications of RFID and NFC. The memory macro with single-poly NVM cell structure fabricated in 0.11μm generic CMOS logic process is proposed and characterized. With unique device and circuitry designs, silicon results demonstrate the write operation with power consumption less than 23μW. In addition, the read operation can be achieved with power consumption less than 3μW at 1MHz access speed and the read voltage down to 0.56V. © 2016 IEEE.

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