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Kahri F.,Electronics and Micro Electronics Laboratory | Mestiri H.,Electronics and Micro Electronics Laboratory | Bouallegue B.,Electronics and Micro Electronics Laboratory | Machhout M.,Electronics and Micro Electronics Laboratory
International Review on Computers and Software | Year: 2014

In modern cryptographic hash function plays an important role. Hash function algorithms are widely used to provide authentication, security and services of integrity. The main computation block in SHA-512 algorithm is governed by a loop with high data dependence for which one implementation strategy is explored in this work as well as design efficiently mapped to hardware architecture. We propose an improved implementation of the SHA-512 hash family, with minimal operator latency, reduced hardware requirements, high frequency, and high throughput. The proposed design were implemented and validated in the FPGA Virtex. The FPGAs targets are XC5VLX30-3ff324, XC6VLX75T-3ff784. © 2014 Praise Worthy Prize S.r.l. - All rights reserved. Source


Mestiri H.,Electronics and Micro Electronics Laboratory | Benhadjyoussef N.,Electronics and Micro Electronics Laboratory | Machhout M.,Electronics and Micro Electronics Laboratory | Tourki R.,Electronics and Micro Electronics Laboratory
International Review on Computers and Software | Year: 2013

Fault injection attacks are powerful cryptanalysis techniques against the Advanced Encryption Standard (AES) algorithm. These attacks are based on injecting faults into the structure of the AES to obtain confidential information. To protect the AES implementation against these attacks, a number of countermeasures have been proposed. In this paper, we proposed a fault detection scheme, based on the information redundancy, for the AES. We discuss the strengths and the weaknesses of this scheme against the fault attacks. Moreover, we conduct a comparative study between fault detection schemes from the literature in terms of fault detection capabilities and implementation cost. The simulation results show that the fault coverage achieves 99.998% for the proposed scheme. Moreover, the proposed detection scheme has been implemented on Xilinx Virtex-5 FPGA. Its fault coverage, area overhead, throughput and frequency degradation have been compared and it is shown that the proposed scheme allows a trade-off between the hardware overhead and the security of the AES. © 2013 Praise Worthy Prize S.r.l. - All rights reserved. Source

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