Engineering Electrical

Engineering, Japan

Engineering Electrical

Engineering, Japan
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Moon Kim Y.,Engineering Electrical | Kameda Y.,Stanford University | Kim H.,Engineering Electrical | Mizuno M.,Stanford University | And 2 more authors.
IEEE Symposium on VLSI Circuits, Digest of Technical Papers | Year: 2010

We present a new low-cost technique for detecting gate-oxide early-life failures (ELF) to overcome reliability challenges in robust systems without requiring expensive concurrent error detection. Our approach is enabled by an on-chip clock control technique, applied during periodic on-line self-test and diagnostics, to detect delay shifts over time before functional failures occur. Using 90nm test chips, we demonstrate the following key results: 1. A gate-oxide ELF transistor inside a combinational logic circuit results in delay shifts over time before functional failures appear. 2. The delay shifts can be successfully detected during on-line self-test and diagnostics using our on-chip clock control technique. © 2010 IEEE.

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