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Verona, Italy

Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2013.3.4 | Award Amount: 9.29M | Year: 2013

Up to now mission & safety critical services of SoS (Systems of Systems) have been running on dedicated and often custom designed HW/SW platforms. In the near future such systems will be accessible, connected with or executed on devices comprising off-the-shelf HW/SW components. Significant improvements have been achieved supporting the design of mixed-critical systems by developing predictable computing platforms and mechanisms for segregation between applications of different criticalities sharing computing resources. Such platforms enable techniques for the compositional certification of applications correctness, run-time properties and reliability.\nCONTREX will complement these important activities with an analysis and segregation along the extra-functional properties real-time, power, temperature and reliability. These properties will be a major cost roadblocks when 1) scaling up the number of applications per platform and the number of cores per chip, 2) in battery powered devices or 3) switching to smaller technology nodes. CONTREX will enable energy efficient and cost aware design through analysis and optimisation of real-time, power, temperature and reliability with regard to application demands at different criticality levels. To reinforce European leadership and industrial competiveness the CONTREX approach will be integrated into existing model-based design methods that can be customized for different application domains and target platforms.\nCONTREX will focus on the requirements derived from the automotive, aeronautics and telecommunications domain and evaluate its effectiveness and drive integration into existing standards for the design and certification based on three industrial demonstrators. Valuable feed-back to the industrial design practice, standards, and certification procedures is pursued.\nOur economic goal is to improve energy efficiency by 20 % and to reduce cost per system by 30 % due to a more efficient use of the computing platform.


Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2009.3.4 | Award Amount: 7.05M | Year: 2009

The main objective of the COMPLEX project is to increase the competitiveness of the European semiconductor, system integrator and EDA industry by addressing the problem of platform-based design space exploration under consideration of power and performance constraints early in the design process. High performance usually causes high power consumption. A main challenge in todays embedded system design is to find the perfect balance between performance and power. This balance can not be found efficiently and at high quality, because until now no generic framework for accurately and jointly estimating performance and power consumption starting at the algorithmic level is available. This can only be achieved in cooperation on a European level, taking into account European platform providers, system developers/integrators, EDA companies, Universities and research institutes from both, the HW and the embedded SW world.
The COMPLEX project will enable the European semiconductor and electronic system industry to achieve a break through in product quality through substantially improved performance and power efficiency. This quantum leap will be achieved by a new design environment for platform-based design-space exploration offering developers of next-generation mobile and embedded systems a highly efficient and productive design methodology and tool chain allowing them to iteratively explore and refine their applications to meet market requirements. The design technology in particular enables the fast simulation and assessment of the platform at Electronic System Level (ESL) with up to cycle accuracy at the earliest instant in the design process. Several new modelling, exploration and simulation concepts will be developed and combined with well established ESL synthesis, cross-compilation, analysis and simulation tools into a seamless holistic design flow enabling performance & power aware virtual prototyping from a combined hardware-software perspective.


Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2011.3.2 | Award Amount: 13.04M | Year: 2011

Smart systems consist of heterogeneous subsystems and components providing different functionalities; they are normally implemented as Multi-Package on a Board. To fully exploit the potential of current nanoelectronics technologies, as well as to enable the integration of existing/new IPs and More than Moore devices, smart system miniaturization and Multi-Chip in a Package implementation are unavoidable. Such goals are only achievable if a flexible software platform (i.e., the SMAC platform) for smart subsystems/components design and integration is made available to designers and system integrators.\nThe platform must include methodologies and EDA tools enabling multi-disciplinary and multi-scale modeling and design, simulation of multi-domain systems, subsystems and components at all levels of abstraction, system integration and exploration for optimization of specific metrics, such as power, performance, reliability and robustness.\nKey ingredients for the construction of the SMAC platform include: (1) The development of a cosimulation and co-design environment which is aware (and thus considers) the essential features of the basic subsystems and components to be integrated. (2) The development of modeling and design techniques, methods and tools that, when added to the platform, will enable multi-domain simulation and optimization at various levels of abstraction and across different technological domains.\nThe SMAC platform will allow to successfully address the following grand challenges related to the design and manufacturing of miniaturized smart systems: (1) Development of innovative smart subsystems and components demonstrating advanced performance, ultra low power and the capability of operating under special conditions (e.g., high reliability, long lifetime). (2) Design of miniaturized and integrated smart systems with advanced functionality and performance, including nanoscale sensing systems, possibly operating autonomously and in a networked fashion


Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2007.3.3 | Award Amount: 3.35M | Year: 2008

Design and verification of modern embedded platforms are two highly related problems which are still mainly addressed by using unrelated methodologies. This effectively reduces development productivity and complicates achieving predictable system properties. The COCONUT project thus focuses on the definition of a formal framework based on a tight integration of design and verification through all refinement steps of an embedded platform design flow, from specifications to logic synthesis and software compilation. In particular, it is intended to propose a modelling and verification flow to enhance and speed-up embedded platform design and configuration with particular regard to application fields related to mixed continuous/discrete models, like for example networked multimedia and sensor network managing. In this context, the main activities of COCONUT will be related to the definition of innovative methodologies and tools to: - define and validate properties that represent the design specification; - automatically synthesize properties into code; - map models between hybrid and discrete domains; - provide correct-by-construction abstraction/refinement processes; - perform post-refinement verification. Such activities will be implemented in a set of tools working on more that one abstraction level whose correctness will be formally proved.

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