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Amrane R.A.,ESI Ecole nationale Superieure dInformatique | Belbachir H.,University of Science and Technology Houari Boumediene
Annales Mathematicae et Informaticae | Year: 2010

Our purpose is to establish that hyperharmonic numbers - successive partial sums of harmonic numbers - satisfy a non-integer property. This gives a partial answer to Mezo{double acute}'s conjecture.


Nadjia A.,Center de Developpement des Technologies Avancees | Mohamed A.,ESI Ecole Nationale Superieure dInformatique
2013 8th IEEE Design and Test Symposium, IDT 2013 | Year: 2013

Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for large operands. It is performed using successive modular multiplications. This paper describes hardware architecture of the m-ary modular exponentiation with reduced number of Montgomery modular multiplications. This architecture has been implemented on FPGA circuit of Virtex-2 and presents best performances in terms of computation time and occupied resources. © 2013 IEEE.


Nadjia A.,Center de Developpement des Technologies Avancees | Mohamed A.,ESI Ecole Nationale Superieure dInformatique
2015 4th International Conference on Electrical Engineering, ICEE 2015 | Year: 2015

Advanced Encryption Standard (AES) is a symmetric cryptographic algorithm used for protecting data. Designing efficient hardware architecture for AES with small hardware resource usage is a challenge. AES uses different data transformations and the most expensive one, in terms of computational resources, is the SubBytes transformation which is carried out by a Look-Up-Table (LUT) named the S-box. In this paper, an efficient implementation of the S-box on LUTs-6 of an FPGA circuit of Virtex-5 is presented. This has reduced both occupied area and execution time, where the reading time of an S-Box is that of one slice. © 2015 IEEE.


Nadjia A.,Center de Developpement des Technologies Avancees | Mohamed A.,ESI Ecole Nationale Superieure dInformatique
12th International Multi-Conference on Systems, Signals and Devices, SSD 2015 | Year: 2015

AES (Advanced Encryption Standard) is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting data. In this paper, we present three hardware architectures for AES, namely Serial/Serial, Parallel /Serial and Parallel/Pipelined. These architectures can be used as IP (Intellectual Property) cores in hybrid cryptosystem RSA-AES implemented on an FPGA PSoC (Programmable System on Chip). The highlights of our work are: implementing S-Box memories of AES SubBytes transformation on Slices of FPGA which reduces the hardware resources and using the Xtime() functions in the implementation of AES MixColumns transformation which accelerate its execution time. Such architectures cater to different applications and offer good tradeoffs between performances and occupied areas. © 2015 IEEE.


Mohamed A.,ESI Ecole Nationale Superieure dInformatique | Nadjia A.,British Petroleum
12th International Multi-Conference on Systems, Signals and Devices, SSD 2015 | Year: 2015

Hash functions play an important role in modern cryptography. They are widely used to provide services of data integrity and authentication. The hash algorithms are based on performing a number of complex operations on the input data that require a significant amount of computing resources especially when the input data are huge. Thus, hardware implementation is far more suitable, for security and performances execution issues, compared to the corresponding software implementations. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. In this paper, we are concerned by optimizing the hardware implementation of the SHA-256 algorithm on virtex-5 Xilinx FPGA. Our main contribution is to design a compact SHA-256 core and to speed-up its critical paths. These are respectively seven and six words addition. The CS (Carry Save) representation is advantageously used to overcome the carry propagation, until the last addition. Special efforts were made to design, at the LUT level, the two components (compressors 7:2 and 6:2) which are the key features of our design; their delay is data path independent and equivalent to the delay of two LUT6. The resulting architecture is compact and operates at 170 MHz with throughput of 1.36 Gbps. © 2015 IEEE.

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