DSPACE GmbH | Date: 2015-08-11
A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.
DSPACE GmbH | Date: 2015-05-27
A method and a device for testing a control unit, in which sensor data are transmitted over a network connection to a real or simulated control unit, which data are calculated by a data processing system using simulation, in which the simulation of the sensor data takes place at least in part with at least one graphics processor of at least one graphics processor unit of the data processing system. The simulated sensor data are encoded in image data that are output via a visualization interface to a data conversion unit that simulates a visualization unit connected to the visualization interface. Via the data conversion unit the received image data are converted into packet data containing the sensor data through the network connection to the control unit.
DSPACE GmbH | Date: 2015-03-06
A computer-implemented method for generating a control program that is executable on a control system from a graphical control model. A better utilization of the control system is achieved in that the graphical control model is translated into program code such that the generated program code has at least one FXP operation and at least one FLP operation, and in that the generated program code is translated into the executable control program such that when the control program is executed on the control system a portion of the control program is executed on the FXP unit and another portion of the control program is executed on the FLP unit.
DSPACE GmbH | Date: 2015-09-22
A method for executing a first application program of a first control unit on a computer, wherein functions for controlling actuators and/or sensors and/or functions for processing and/or providing data from actuators and/or sensors are executed by the first application program. A first interface between a control unit hardware and a first application program of the control unit is established by the control unit operating system. A first virtual control unit operating system and a first virtual application program are generated by compilation. A simulation environment interface is made available by the simulation environment for transfer of a data item and/or of an event to the first virtual application program and/or the virtual control unit operating system. The simulation environment initiates and controls an execution of the first virtual application program within the control unit operating system within the first virtual machine through the simulation environment interface.
DSPACE GmbH | Date: 2015-09-24
A method for automatically determining models signals of an FPGA program which are readable from the FPGA with the aid of a readback following an FPGA build, including the following steps: generating an FPGA model and generating an FPGA code from the FPGA model, the method comprising the additional step of an automatic analysis for the purpose of identifying signals which are readable from the FPGA with the aid of a readback, prior to the completion of the step of generating the FPGA code from the FPGA model, and the method comprises the step of outputting signals which are readable from the FPGA with the aid of a readback. A data processing device is also provided for carrying out the method.