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Kim S.,Korea University | Kim H.,Korea University | Kim D.-H.,Korea University | Jeon S.,Korea University | And 2 more authors.
IEICE Transactions on Electronics | Year: 2011

In this work, a V-band low noise amplifier (LNA) is developed in a commercial 0.13 μm RFCMOS technology. Common-source (CS) topology, known to show a better noise performance than the cascode topology, was adopted and 4-stage was employed to achieve a sufficient gain at the target frequency near the cutoff frequency fT . The measured gain was 18.6 dB with VDD = 1.2V and increased up to 20.2 dB with VDD = 1.8V at 66 GHz. The measured NF showed a minimum value of 7.0 dB at 62 GHz. DC power consumption was 24mW with VDD = 1.2V. The size of the fabricated circuit is as compact as 0.45mm × 0.69 mm. This work was further extended to investigate the effect of dummy fills on LNA performance. An identical LNA, except for the dummy fills formed very close to (and under) the metal lines of spiral inductors and interconnects, was also fabricated and compared with the standard LNA. A peak gain degradation of 3.6 dB and average NF degradation of 1.3 dB were observed, which can be ascribed to the increased mismatch and line loss due to the dummy fills. Copyright © 2011 The Institute of Electronics, Information and Communication Engineers.


Song J.,Dongbu HiTek
Solid State Technology | Year: 2012

A 700V DR-LDMOS (Double RESURF LDMOS) transistor is optimized by using thin n-epi technology and introducing a P-TOP layer to reduce on-resistance while maintaining high breakdown voltage. The high on-breakdown voltage transfers a low voltage logic signal to a high voltage control part. As the P-TOP length decreases towards P-BODY edge, the on-resistance is increased due to the reduced conductivity caused by increases in JFET resistance. As a result of optimizing JFET resistance for DR-LDMOS, an on-breakdown exceeding 700V is achievable at the optimal condition and the off-breakdown voltage exceeds 900V. Source corner region (A) breakdown voltage is decreased dramatically due to the high surface electric field under the gate electrode caused by a broken charge balance between n-epi and P-TOP.


Young B.,Oregon State University | Kwon S.,Dongbu HiTek | Elshazly A.,Oregon State University | Hanumolu P.K.,Oregon State University
Proceedings of the Custom Integrated Circuits Conference | Year: 2010

A time-to-digital converter (TDC) employs a phase-reference second-order continuous-time delta-sigma modulator to achieve high resolution and low power. The modulator operates on the phase of the input signal and generates an equivalent noise-shaped one-bit output data stream. Fabricated in an LP 90nm CMOS process, the prototype TDC achieves better than 2.4ps resolution over a 3.2ns range in a 1MHz signal bandwidth while consuming 2.1mW from a 1.2V supply. © 2010 IEEE.


Hutter L.,Dongbu HiTek | James F.,Dongbu HiTek
Solid State Technology | Year: 2010

Power management is one of the hottest areas in semiconductors today. The ironic thing about the semiconductor industry (well-known to the analog guys) is this: the more the world goes 'digital', the more demand there is for analog ICs. That's because the real world is analog, so connecting the real world to the digital signal processors or microprocessors, which are at the heart of most electronic systems today, requires a variety of analog chips to condition and convert the signals between the analog and digital domains. At the heart of all this are power management chips. This article discusses the technical requirements for power management chips and trends going forward.


Choi Y.,Hanyang University | Tak W.,Hanyang University | Yoon Y.,Hanyang University | Roh J.,Hanyang University | And 2 more authors.
IEEE Journal of Solid-State Circuits | Year: 2012

A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm 2 and achieves a THD+N of 0.018%. © 2011 IEEE.

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