Dongbu HiTek

South Korea

Dongbu HiTek

South Korea
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Park I.-Y.,Dongbu HiTek | Choi Y.-K.,Dongbu HiTek | Ko K.-Y.,Dongbu HiTek | Shim S.-C.,Dongbu HiTek | And 4 more authors.
8th International Conference on Power Electronics - ECCE Asia: "Green World with Power Electronics", ICPE 2011-ECCE Asia | Year: 2011

This paper reviews the technology trends of BCD (Bipolar-CMOS-DMOS) technology in terms of voltage capability, switching speed of power transistor, and high integration of logic CMOS for SoC (System-on-Chip) solution requiring high-voltage devices. Recent trends such like modularity of the process, power metal routing, and high-density NVM (Non-Volatile Memory) are also discussed. © 2011 IEEE.

Hutter L.,Dongbu HiTek | James F.,Dongbu HiTek
Solid State Technology | Year: 2010

Power management is one of the hottest areas in semiconductors today. The ironic thing about the semiconductor industry (well-known to the analog guys) is this: the more the world goes 'digital', the more demand there is for analog ICs. That's because the real world is analog, so connecting the real world to the digital signal processors or microprocessors, which are at the heart of most electronic systems today, requires a variety of analog chips to condition and convert the signals between the analog and digital domains. At the heart of all this are power management chips. This article discusses the technical requirements for power management chips and trends going forward.

Nah H.,Dongbu Hitek | Kim J.-H.,Dongbu Hitek | Lee C.-E.,Dongbu Hitek | Joung T.-Y.,Dongbu Hitek | And 3 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2016

ESD characteristics of the UHV resistors (UHVRs) has been studied. The UHVR under study suffers from a low ESD level. The failure analysis has been done with the aid of TLP measurements and simple equivalent circuit simulations. From the analysis, a transient large voltage difference on the field oxide due to the RC delay by the large resistance and the parasitic capacitances of UHVR has been found to be the cause of the low ESD level. Finally, it has been shown that the reduction of RC delay by the decrease of the parasitic capacitances, which was possible through a simple layout modification, can improve the ESD performance of the UHVR. © 2016 IEEE.

Choi Y.,Hanyang University | Tak W.,Hanyang University | Yoon Y.,Hanyang University | Roh J.,Hanyang University | And 2 more authors.
IEEE Journal of Solid-State Circuits | Year: 2012

A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm 2 and achieves a THD+N of 0.018%. © 2011 IEEE.

Kim S.,Korea University | Kim H.,Korea University | Kim D.-H.,Korea University | Jeon S.,Korea University | And 2 more authors.
IEICE Transactions on Electronics | Year: 2011

In this work, a V-band low noise amplifier (LNA) is developed in a commercial 0.13 μm RFCMOS technology. Common-source (CS) topology, known to show a better noise performance than the cascode topology, was adopted and 4-stage was employed to achieve a sufficient gain at the target frequency near the cutoff frequency fT . The measured gain was 18.6 dB with VDD = 1.2V and increased up to 20.2 dB with VDD = 1.8V at 66 GHz. The measured NF showed a minimum value of 7.0 dB at 62 GHz. DC power consumption was 24mW with VDD = 1.2V. The size of the fabricated circuit is as compact as 0.45mm × 0.69 mm. This work was further extended to investigate the effect of dummy fills on LNA performance. An identical LNA, except for the dummy fills formed very close to (and under) the metal lines of spiral inductors and interconnects, was also fabricated and compared with the standard LNA. A peak gain degradation of 3.6 dB and average NF degradation of 1.3 dB were observed, which can be ascribed to the increased mismatch and line loss due to the dummy fills. Copyright © 2011 The Institute of Electronics, Information and Communication Engineers.

Song J.,Dongbu HiTek
Solid State Technology | Year: 2012

A 700V DR-LDMOS (Double RESURF LDMOS) transistor is optimized by using thin n-epi technology and introducing a P-TOP layer to reduce on-resistance while maintaining high breakdown voltage. The high on-breakdown voltage transfers a low voltage logic signal to a high voltage control part. As the P-TOP length decreases towards P-BODY edge, the on-resistance is increased due to the reduced conductivity caused by increases in JFET resistance. As a result of optimizing JFET resistance for DR-LDMOS, an on-breakdown exceeding 700V is achievable at the optimal condition and the off-breakdown voltage exceeds 900V. Source corner region (A) breakdown voltage is decreased dramatically due to the high surface electric field under the gate electrode caused by a broken charge balance between n-epi and P-TOP.

Kim J.-H.,Dongbu HiTek | Kim J.-J.,Dongbu HiTek | Lee K.-O.,Dongbu HiTek | Lee C.-E.,Dongbu HiTek | And 4 more authors.
2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2012 - Digest of Papers | Year: 2012

Flicker (1/f) noise and TCR are compared for arsenic- and phosphorus-doped polysilicon in a 0.18 μm CMOS base technology. Resistors implanted with arsenic exhibit about 4 times higher noise than with phosphorus at the same dose and thermal budget. The TCR of arsenic-doped polysilicon is negative, near -1065 ppm/K, while that of phosphorus-doped resistors positive, about + 590 ppm/K. The mismatch of N-channel MOSFETs with arsenic-doped gates is about 40% lower than with phosphorus gates. The results are attributed to the difference in grain-size and dopant segregation. The difference in grain size is confirmed by TEM and SEM micrographs. © 2012 IEEE.

Young B.,Oregon State University | Kwon S.,Dongbu HiTek | Elshazly A.,Oregon State University | Hanumolu P.K.,Oregon State University
Proceedings of the Custom Integrated Circuits Conference | Year: 2010

A time-to-digital converter (TDC) employs a phase-reference second-order continuous-time delta-sigma modulator to achieve high resolution and low power. The modulator operates on the phase of the input signal and generates an equivalent noise-shaped one-bit output data stream. Fabricated in an LP 90nm CMOS process, the prototype TDC achieves better than 2.4ps resolution over a 3.2ns range in a 1MHz signal bandwidth while consuming 2.1mW from a 1.2V supply. © 2010 IEEE.

Moon N.-C.,Dongbu Hitek | Kwon K.-W.,Dongbu Hitek | Lee C.-J.,Dongbu Hitek | Sung K.-S.,Dongbu Hitek | And 3 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2013

For high side gate driver IC, we applied to single p-type isolation technic between high side region and 700V LDMOS (lateral double-diffused MOS) drain to reduce electric potential of junction termination by the crossing drain metal of 700V LDMOS. This single p-type isolation has low doping concentration to be fully depleted for maintaining a high voltage, normally more than 700V. It is limited to remove the cross-talk problem caused by leakage current between high side region and drain of 700V LDMOS in HVIC (High Voltage Integrated Circuits) using self-shielding structure. So, we are proposed to multi-ring p-type isolation technic to clear leakage issue between two LDMOS used as level shifters. And a robust high side gate driver IC adapting new self-shielding concept with perfect isolation using p-type multi-ring structure is experimentally realized. Experiment results have shown that over 850V breakdown voltage and no leakage current between LDMOS drain and high side region even though the drain voltage of LDMOS is lower than 2V. In addition, highly doped n+ buried layer in the high side region of proposed structure led good dV/dt immunity. © 2013 IEEE.

Yoon J.,University of Seoul | Lee S.,University of Seoul | Kim J.,University of Seoul | Song N.,Dongbu HiTek | And 2 more authors.
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS | Year: 2010

In this paper, the amplifier path consisting of the low-noise amplifier (LNA) and programmable-gain amplifier (PGA) is designed. For lower input-referred noise power, the active input impedance termination should be indispensable. The novel circuit is proposed for high-performance LNA. The PGA is designed to cover the operating range of 48dB. The analog front-end is designed and verified in a 0.18-μm CMOS technology. Power dissipation is 56mW for a single supply voltage of 1.8V. © 2010 IEEE.

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