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Kambhampati S.,Dhanekula Institute of Engineering and Technology
Proceedings of the International Conference on Inventive Computation Technologies, ICICT 2016 | Year: 2017

In signal processing systems, the fundamental computation is nothing but convolution which is found in many application areas. The main building blocks are the multipliers to calculate convolution. But multipliers are the main power consuming elements. In recent years power is an important constraint. Now days, linear convolution has been implemented using distinct types of multipliers to decrease power dissipation. In this paper, modulo linear convolution have been proposed using modulo multipliers based on Radix-8 booth encoding algorithm for bits n=8, 16, 32 and 64. The modulo design is coded in Verilog HDL, Xilinx 14.7 has been used to perform Simulation and Synthesis. The proposed technique efficiently speeds up the computation which in turn decreases power dissipation, hardware resources and area significantly.


Prasad J.V.,Dhanekula Institute of Engineering and Technology
2013 International Conference on Energy Efficient Technologies for Sustainability, ICEETS 2013 | Year: 2013

In deregulated power systems, maintenance of sufficient security margin and reliability level are the major tasks of the independent system operator (ISO). The provision of bids change at any time in the competitive market makes the power injections and withdrawals are time variant and are mainly determined based on economic grounds only. In order to maintain security and reliability, the adjustable markets and ancillary service markets are also becomes an integral part in the general power market clearing mechanisms. This paper is addressing the combined market model to assess the spinning reserve (SR). The deterministic approach is adapted to require SR in the system. The competitive power market is applied to all the markets independently and later they are integrated in to one common optimal solution. The proposed approach is discussed on IEEE-14 bus system. © 2013 IEEE.


Ram I.S.,Dhanekula Institute of Engineering and Technology | Kota V.R.,Jawaharlal Nehru Technological University Kakinada
Journal of Circuits, Systems and Computers | Year: 2016

In this paper, a novel GSA technique is used for improving the voltage stability of the system with multiple FACTS devices. The proposed novel algorithm is used to optimize the location, size and number of FACTS devices. The GSA is enhanced with the use of boundary for optimizing the parameters of the system. Therefore, the voltage stability is improved while satisfying a given set of operating and physical constraints. Here, multiple FACTS devices are used to evaluate the performance of proposed algorithm and these devices are connected in single line and double line of the bus system. The optimal locations and power ratings of the FACTS devices are determined, based on the voltage collapse rating and power loss of the system. The proposed technique is implemented in MATLAB platform and tested with IEEE 30 bus system. The performance of the proposed method is evaluated by locating multiple FACTS devices and compared with the PSO-adaptive GSA and GA-GSA technique. © 2016 World Scientific Publishing Company


Ram I.S.,Dhanekula Institute of Engineering and Technology | Amarnath J.,Jawaharlal Nehru Technological University
2013 Nirma University International Conference on Engineering, NUiCONE 2013 | Year: 2013

This paper mainly focused on improvement of voltage stability of the power transmission system with voltage collapse concern. To achieve this, Flexible AC Transmission System (FACTS) devices are suggested to be installed properly in the network. Among all the FACTS devices, the combined compensator such as Inter line power flow controller (IPFC) is considered for its greater flexibility in power control. The primary function of IPFC is to improve transmission system voltage profile, thereby enhancing the voltage stability. The hybrid algorithm is formed by the combination of genetic algorithm (GA) and gravitational search algorithm (GSA) for optimal setting of IPFC. Initially according to the variation of power loss and voltage collapse index, the optimal locations suitable for IPFC installation are determined by genetic algorithm (GA). Among the optimal locations, the maximum combinations of the transmission lines of corresponding buses are analyzed. Then the injecting voltage magnitude and angle of IPFC is determined by GSA algorithm. From the values, exact rating of IPFC real and reactive powers is calculated to inject at that optimal location. Finally, the optimal power rating of IPFC is injected to the optimized location. The power flow is analyzed by Newton-Raphson method before and after insertion of IPFC. The proposed method is implemented in MATLAB working platform on IEEE-30 bus system and the results show that the proposed method gives a quick solution for optimal setting of IPFC in transmission system and consequently the voltage stability of the system is also improved. © 2013 IEEE.


Ram I.S.,Dhanekula Institute of Engineering and Technology | Amarnath J.,Jawaharlal Nehru Technological University
2013 Nirma University International Conference on Engineering, NUiCONE 2013 | Year: 2013

The voltage collapse problem can avoid by providing proper reactive power resources to maintain specified voltage profile in the network. The traditional approaches are not sufficient to mitigate reactive power imbalance in the modern power system. Hence one of the emerging technologies like integration of Flexible AC Transmission System (FACTS) devices has been adopted in this paper. A hybrid algorithm is proposed to improve voltage stability of power system and to optimize the FACTS controllers. This Hybrid algorithm intended by the combination of genetic algorithm (GA) and gravitational search algorithm (GSA). For the implementation of this technique, one of the FACTS devices namely Unified power flow controller (UPFC) is selected. The GA is applied to identify best locations of UPFC and later GSA is implemented to optimize UPFC ratings in a sequential manner. The proposed method is implemented on IEEE-30 bus system using MATLAB working platform. The results have shown the effectiveness of proposed algorithm for practical applications. © 2013 IEEE.


Shanmukharao L.,Dhanekula Institute of Engineering and Technology | Ramana N.V.,JNTUH College of Engineering
PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems | Year: 2012

In this paper three control areas are considered, each area contains one hydro and one thermal system. All the three areas are connected with the help of HVDC link. Automatic Generation Control (AGC)problem formulation is affected with open transmission access and evaluation of more socialized companies for generation, transmission and distribution. Therefore conventional three area system is modified so that it will consider the effect of bilateral contract on dynamics. Dynamic analysis is carried out on three area hydrothermal system with HVDC link as well as with AC tie line. It is observed that dynamic response of three area hydro thermal system connected with AC tie line is sluggish and degraded compared with HVDC link. © 2012 IEEE.


Krishna R.S.S.M.R.,Dhanekula Institute of Engineering and Technology | Mal A.K.,National Institute of Technology Durgapur
International Conference on Microelectronics, Computing and Communication, MicroCom 2016 | Year: 2016

Adders outline a fundamental bit of just about every modern-day integrated circuit inferable from their thorough application in productive execution of parallel calculating. The design constraints of a basic adder topology are beyond question quicker operational speed, tolerable power consumption as well as effectively cheaper on chip space. This work compares the performance of various adder topologies in terms of timing slack (critical path), power and area. The adder topology used in this work are Ripple Carry Adder, Carry Look ahead Adder, Carry Skip Adder and Carry Select Adder. The designs are synthesized at sub-micron and deep sub-micron technologies like gpdk180 and gpdk090, gpdk045 and also intended for Low Power VLSI the designs are exclusively synthesized at Low VT, High VT and Back-Bias standard cells of gpdk045 using Encounter RTL Compiler. The functionality of the designs is confirmed utilizing Incisive Unified Simulator. Then Physical realization is carried out victimizing Encounter Digital Implementation. © 2016 IEEE.


Krishna R.S.S.M.R.,Dhanekula Institute of Engineering and Technology | Madhumati G.L.,Dhanekula Institute of Engineering and Technology | Mal A.K.,National Institute of Technology Durgapur
International Conference on Microelectronics, Computing and Communication, MicroCom 2016 | Year: 2016

Switched Capacitor (SC) techniques have grown to be the de facto standard for implementation of blended signal blocks in modern CMOS VLSI. The performance regarding switched capacitor circuits enormously be determined by the productive design of Non Overlapping Clock (NOC). Standard NOC generator circuits offered within the literature build use of delay circuits realised victimizing standard CMOS inverters hooked up within a chain. With regard to modest and large frequencies, the actual amounts of inverters tend to be small. Nevertheless power and area constraints limit the employment of ordinary CMOS inverter as delay block, throughout lower frequency applications. In this particular work it can be recommended to utilize voltage scaled CMOS inverter along with Transmission Gate (TG) blend as unit delay block for achieving substantial delay. Designs are simulated on Generic 180 nm 1.8 V 1P 6M Process Design Kit (gpdk180) using Cadence Virtuoso Design Environment. Simulation results conferred right here solidly bolster the investigation done all through the work. PVT analysis affirms the particular rigidity on the architectural mastery. © 2016 IEEE.


Prasad J.V.,Dhanekula Institute of Engineering and Technology | Sekhar K.C.,P.A. College
Proceedings of 2013 International Conference on Power, Energy and Control, ICPEC 2013 | Year: 2013

Currently, most of the power systems operate under deregulation environment. This mode of operation leads the power systems in to unpredictable and sometimes unsecured states with the competition among market participants in addition to the uncertainties. The maintenance of acceptable range of bus voltage magnitudes and transmission congestion management are become essential preventive tasks to the system operator to drive the competitive electricity market schedule. Due to the lack of reactive power support and transmission system capacity, the networks could also subject to voltage instability. In order to improve the transmission system loadability even under line outage contingencies, this paper addressing the application of flexible ac transmission system (FACTS) devices. Based on the impact on critical loading margin (CLM), the contingencies have been ranked. The critical loading margin is determined using repeated power flow (RPF) method and possible improvement is achieved with various FACTS devices in the network. SVC, TCSC, TCPST and UPFC devices have been considered to install in the network. © 2013 IEEE.


Shanmukha Rao L.,Dhanekula Institute of Engineering and Technology | Ramana N.V.,JNTUH College of Engineering
International Review on Modelling and Simulations | Year: 2013

This paper deals with major problem of load frequency control in two area deregulated hydro thermal system and unveils a new solution called sliding mode control strategy as an advanced technique. The proposed new control strategy will manage nonlinearities and uncertainties in the measurement of certain system states of the highly non linear power system. This optimal sliding mode controller tested on two area hydro thermal deregulated power system that includes bilateral contact when the system undergoes sudden disturbance. The performance of proposed new Optimal sliding mode controller has been compared with sliding mode observer based optimal controller and Conventional PI controller. © 2013 Praise Worthy Prize S.r.l. - All rights reserved.

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