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Porto Alegre, Brazil

Cortes F.P.,Design Center Semiconductors | Brito J.P.M.,Design Center Semiconductors | Ghignatti E.,Design Center Semiconductors | Olmos A.,Design Center Semiconductors | And 2 more authors.
Analog Integrated Circuits and Signal Processing | Year: 2015

This paper presents a low power, low voltage power management (PM) system for low-frequency passive RFID tags in a standard CMOS 0.18 µm technology. Passive tags have no internal power source but use the incoming RF energy transmitted by a transceiver to power all the circuitry inside them via a rectifier. Due to the wide variation of the rectified voltage as a function of the RF power, two stages of regulation are required: a shunt regulator working as limiter (3 V) at the rectifier output, and a LDO regulator at a tighter range of 1.15 V. Besides that, two blocks monitor the available RF power at the LDO regulated output and flag when the power is low for different tag operation modes: power-on reset during a read event, and power flag during a write event. All blocks rely on a low power resistor-less 3.5 nA current reference and a 400 mV voltage reference. Both references make use of the self cascode MOSFET structure. The complete PM system is functional with 2 µA current. © 2015, Springer Science+Business Media New York. Source

Olmos A.,Design Center Semiconductors | Pablo J.,Design Center Semiconductors | Brito M.,Design Center Semiconductors | Jorge F.,Design Center Semiconductors | And 3 more authors.
SBCCI 2014: Proceedings of the 27th Symposium on Integrated Circuits and Systems Design | Year: 2014

This paper presents the design of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. Besides that, the two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a 0.18?m standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA. The complete circuit including the current source and the 2-transistor Self-Cascode MOSFET occupies an area of 0.01mm2. © 2014 IEEE. Source

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