Ann Arbor, MI, United States

Reveal Design Automation, Inc.

www.reveal-da.com
Ann Arbor, MI, United States

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Trademark
Reveal Design Automation, Inc. | Date: 2014-04-15

Software for use in the field of design automation that analyzes integrated circuits for the purpose of detecting design flaws.


Grant
Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 149.91K | Year: 2012

This Small Business Innovation Research Phase I Project addresses the challenge of automating and scaling formal equivalence verification between architectural ESL/TLM SystemC models and RTL Verilog models for microprocessors and ASIC microcontrollers. The complexity of industrial processors, together with the differences in semantics of SystemC and Verilog, create a significant modeling gap that makes it infeasible to verify RTL Verilog implementations against their SystemC specification models. This gap impedes the progression currently taking place in EDA, wherein designers are moving upwards in the abstraction level for modeling and verifying hardware designs. Our formal equivalence verification technology will allow automatically obtaining RTL from ESL models using high-level synthesis tools, and formally verifying the correctness of the resulting models against the specification models. It will also allow manually written RTL models to be verified against ESL models originally created for architectural simulation. Expected challenges include overcoming the spatial and temporal modeling gaps, and verifying equivalence for an unlimited depth using finite equivalence formulations. By end of project, we anticipate to prototype a software program that will discover unintended behavior in microprocessor designs by ARM with respect to the reference architecture, or prove the lack of any bugs, with modest computational resources. Functional verification of microprocessor designs remains a key challenge for the industry due to exponentially growing verification costs - typically>50% of a design budget. Formal verification has potential to reduce these costs, however existing formal technology can only handle small RTL blocks and is only used by a handful of formal domain experts. With the industry shifting towards larger design blocks and higher-level ESL languages such as SystemC, a turn-key tool such as ours is necessary to bridge the ESL/RTL verification gap and addresses the needs of design and verification engineers who do not necessarily have formal domain expertise. Our target market includes both the integrated design manufacturing and fabless ASIC/SoC suppliers. A typical customer would be an ASIC design company looking to lower verification costs, decrease time-to-market, and reduce the risks of discovering errors during post-silicon verification or post-production. Formal semiconductor verification tools such as ours play an especially vital role in mission-critical semiconductor design markets such as ASICs for medical equipment, high-availability sensors, and automotive semiconductors. Our long-term goal is to make formal verification technologies scalable and directly usable by designers at higher abstraction levels, enabling exponential growth in design complexity without exponential growth in verification cost.


Grant
Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 720.64K | Year: 2013

This Small Business Innovation Research (SBIR) Phase II project addresses the challenge of automating and scaling formal equivalence verification between architectural SystemC models and RTL Verilog models for microprocessors and ASIC microcontrollers. The complexity of industrial processors, together with the differences in semantics of SystemC and Verilog, create a significant modeling gap that makes it infeasible to verify RTL Verilog implementations against their SystemC specification models. This gap impedes the progression currently taking place in EDA, wherein designers are moving upwards in the abstraction level for modeling and verifying hardware designs. Our formal equivalence verification technology will allow automatically obtaining RTL from ESL models using high-level synthesis tools, and formally verifying the correctness of the resulting models against the specification models. It will also allow manually written RTL models to be verified against ESL models originally created for architectural simulation. Expected challenges include overcoming the spatial and temporal modeling gaps, and verifying equivalence for an unlimited depth using finite equivalence formulations. By end of project, we anticipate to prototype a software program that will represent a product for architectural validation of general purpose microcontrollers, capable of proving equivalence or finding bugs with reasonable computational resources. The broader impact/commercial potential of this project is to make formal verification technologies scalable and directly usable by designers at higher abstraction levels, enabling exponential growth in design complexity without exponential growth in verification cost. The products resulting from this project will provide substantial benefit by ensuring design correctness for mission-critical components such as implantable medical devices, aviation hardware, and satellite/space systems. In addition to hardware verification, the work done in this project will contribute to firmware and software verification, which has utilized similar techniques in the past. It will additionally contribute to exploring industrial-oriented algorithms and heuristics in the domain of automated reasoning and constraint satisfaction problems, used in theorem proving, machine learning, scheduling optimization, gaming, and network security.


Patent
Reveal Design Automation, Inc. | Date: 2013-06-04

The use of Xs in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.


Grant
Agency: NSF | Branch: Standard Grant | Program: | Phase: SMALL BUSINESS PHASE I | Award Amount: 149.91K | Year: 2012

This Small Business Innovation Research Phase I Project addresses the challenge of automating and scaling formal equivalence verification between architectural ESL/TLM SystemC models and RTL Verilog models for microprocessors and ASIC microcontrollers. The complexity of industrial processors, together with the differences in semantics of SystemC and Verilog, create a significant modeling gap that makes it infeasible to verify RTL Verilog implementations against their SystemC specification models. This gap impedes the progression currently taking place in EDA, wherein designers are moving upwards in the abstraction level for modeling and verifying hardware designs. Our formal equivalence verification technology will allow automatically obtaining RTL from ESL models using high-level synthesis tools, and formally verifying the correctness of the resulting models against the specification models. It will also allow manually written RTL models to be verified against ESL models originally created for architectural simulation. Expected challenges include overcoming the spatial and temporal modeling gaps, and verifying equivalence for an unlimited depth using finite equivalence formulations. By end of project, we anticipate to prototype a software program that will discover unintended behavior in microprocessor designs by ARM with respect to the reference architecture, or prove the lack of any bugs, with modest computational resources.

Functional verification of microprocessor designs remains a key challenge for the industry due to exponentially growing verification costs - typically >50% of a design budget. Formal verification has potential to reduce these costs, however existing formal technology can only handle small RTL blocks and is only used by a handful of formal domain experts. With the industry shifting towards larger design blocks and higher-level ESL languages such as SystemC, a turn-key tool such as ours is necessary to bridge the ESL/RTL verification gap and addresses the needs of design and verification engineers who do not necessarily have formal domain expertise. Our target market includes both the integrated design manufacturing and fabless ASIC/SoC suppliers. A typical customer would be an ASIC design company looking to lower verification costs, decrease time-to-market, and reduce the risks of discovering errors during post-silicon verification or post-production. Formal semiconductor verification tools such as ours play an especially vital role in mission-critical semiconductor design markets such as ASICs for medical equipment, high-availability sensors, and automotive semiconductors. Our long-term goal is to make formal verification technologies scalable and directly usable by designers at higher abstraction levels, enabling exponential growth in design complexity without exponential growth in verification cost.


Grant
Agency: NSF | Branch: Standard Grant | Program: | Phase: SMALL BUSINESS PHASE II | Award Amount: 871.85K | Year: 2013

This Small Business Innovation Research (SBIR) Phase II project addresses the challenge of automating and scaling formal equivalence verification between architectural SystemC models and RTL Verilog models for microprocessors and ASIC microcontrollers. The complexity of industrial processors, together with the differences in semantics of SystemC and Verilog, create a significant modeling gap that makes it infeasible to verify RTL Verilog implementations against their SystemC specification models. This gap impedes the progression currently taking place in EDA, wherein designers are moving upwards in the abstraction level for modeling and verifying hardware designs. Our formal equivalence verification technology will allow automatically obtaining RTL from ESL models using high-level synthesis tools, and formally verifying the correctness of the resulting models against the specification models. It will also allow manually written RTL models to be verified against ESL models originally created for architectural simulation. Expected challenges include overcoming the spatial and temporal modeling gaps, and verifying equivalence for an unlimited depth using finite equivalence formulations. By end of project, we anticipate to prototype a software program that will represent a product for architectural validation of general purpose microcontrollers, capable of proving equivalence or finding bugs with reasonable computational resources.

The broader impact/commercial potential of this project is to make formal verification technologies scalable and directly usable by designers at higher abstraction levels, enabling exponential growth in design complexity without exponential growth in verification cost. The products resulting from this project will provide substantial benefit by ensuring design correctness for mission-critical components such as implantable medical devices, aviation hardware, and satellite/space systems. In addition to hardware verification, the work done in this project will contribute to firmware and software verification, which has utilized similar techniques in the past. It will additionally contribute to exploring industrial-oriented algorithms and heuristics in the domain of automated reasoning and constraint satisfaction problems, used in theorem proving, machine learning, scheduling optimization, gaming, and network security.


Patent
Reveal Design Automation, Inc. | Date: 2015-08-13

The use of Xs in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.


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Reveal Design Automation, Inc. | Entity website

Reveal®: EXhaustive Verification Made Possible Our products empowers you to take on complexsystem implementationsand iterate faster while having the full confidence of Formal Verification

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