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Schmidt C.,DCG Systems GmbH | Wadhwa K.,DCG Systems | Reverdy A.,Sector Technologies SAS | Reinders E.,MASER Engineering B.V.
IEEE International Reliability Physics Symposium Proceedings | Year: 2013

Within this paper, the method of Lock-in Thermography (LIT) is presented and introduced as an useful method for localizing electrical active defects caused by reliability-related failure mechanism. After a short introduction of the physical principle, several case studies are presented. © 2013 IEEE.


Forli L.,LFoundry | Picart B.,LFoundry | Reverdy A.,Sector Technologies | Schlangen R.,DCG Systems
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2011

In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect. Copyright © 2011 ASM International®. All rights reserved.


Seimiya N.,MARUBUN CPRPORATION | Watanabe T.,Kanagawa University | Ichinomiya T.,DCG Systems
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2013

We developed the non-destructive failure analysis method that is combination of Lock-in thermography (LIT) and high resolution 3D oblique CT. It made possible to complete the total analysis efficiently, because we can distinguish the type of failure by this non-destructive method. Copyright © 2013 ASM International® All rights reserved.


Seimiya N.,Marubun Corporation | Watanabe T.,Kanagawa University | Ichinomiya T.,DCG Systems
Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA | Year: 2013

We developed the non-destructive failure analysis method that is combination of Lock-in thermography (LIT) and high resolution 3D oblique CT. It made possible to complete the total analysis efficiently, because we can distinguish the type of failure by this non-destructive method. © 2013 IEEE.


Kindereit U.,IBM | Weger A.J.,IBM | Stellari F.,IBM | Song P.,IBM | And 3 more authors.
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2012

In this paper, near-infrared photon emission spectroscopy measurements from ring oscillators in 45 nm and 32 nm SOI process technology are compared. Employing a cryogenically cooled camera, the measurements cover a broad spectral range from 1200-2200 nm. Both leakage and switching emission, increase monotonically with the wavelength, suggesting measurements should be made at longer wavelengths than has historically been practiced. The paper discusses the optimum cut-off wavelength for maximum signal-to-noise ratio and the obvious importance of reduced ambient temperature for performing measurements. Copyright © 2012 ASM International® All rights reserved.


FEI Co., Hillsboro, Ore., has acquired DCG Systems, Fremont, Calif., a leading supplier of electrical fault characterization, localization, and editing equipment for a wide range of semiconductor and electronics manufacturers. The deal combines FEI's leading physical failure analysis capabilities for the semiconductor lab with DCG's complementary portfolio of electrical failure analysis solutions. DCG's offerings expand FEI's served available market through the addition of optical imaging, thermal imaging, and nano-probing technologies.  The combined company's solutions will offer a more complete workflow for customers as they deal with the increasing complexities from process development to advanced 3D packaging. "The acquisition of DCG expands FEI's presence and capability in the semiconductor lab and enhances our ability to provide a complete workflow solution," commented Don Kania, president and CEO of FEI. "The combination brings together leaders in physical and electrical failure analysis and will enable our customers to better connect workflows to improve time to data and efficiency." "Together with FEI we have a tremendous opportunity to offer our customers an integrated defect analysis solution," commented Israel Niv, CEO of DCG. "The DCG team is excited to join forces with FEI and tap into FEI's strong global presence and significant R&D capabilities to drive further penetration of DCG's leading electrical failure analysis solutions.  We look forward to working together with FEI to provide integrated solutions to help our customers successfully execute on their future technology roadmaps." DCG generated revenue of $76 million in its fiscal year ended January 31, 2015.  The transaction is expected to be slightly accretive to FEI's 2016 GAAP EPS.  FEI intends to fund the acquisition with cash on hand.


Kimball M.,Maxim Integrated Products Inc. | Nemirow C.,DCG Systems
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2012

Failure analysis of RFICs can be a challenging problem, particularly as frequencies ascend into the medium to high GHz region. As frequency goes up, active probes become less and less accurate due to capacitive loading of circuit nodes, and capacitive coupling of stray signals into the probe from nearby circuit traces. We have found that Laser Voltage Imaging (LVi) offers an alternative measurement technique that can avoid these problems. But our work also showed that there are unusual failure signatures which appear as signal frequencies go up. A combination of LVI and RF-SDL was found to yield the best result. Copyright © 2012 ASM International® All rights reserved.


Ng Y.S.,Nvidia | Marks H.,Nvidia | Nemirov C.,DCG Systems | Tsao C.-C.,DCG Systems | Vickers J.,DCG Systems
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2013

Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented. Copyright © 2013 ASM International® All rights reserved.


Lundquist T.,DCG Systems
Electronic Device Failure Analysis | Year: 2011

The Institute of LSI Testing held its 30th annual LSI Testing Symposium (LSITS) in Osaka, Japan, between November 10-12, 2010. The symposium was focused on progress in measurements to cover the complete cycle ranging from test design, manufacturing process, test fault diagnosis, back to process and design improvement. The event was attended by 345 attendees and offered three days of platform presentations where session topics included metrology defect inspection, topography for 3-D devices, novel microscopy techniques, IC-level debug and diagnosis, localization techniques and applications, and circuit edit, nanoprobing. Papers of special interest to EDFAS members were presented in the session on no-bias analysis techniques and included a paper entitled 'Failure Analysis Method Using a Target Excitation, Quasi-Electrostatic Field Sensing Technique.


Malik T.,DCG Systems | Jain R.,DCG Systems | Meijer F.,MASER Engineering | Velthof T.,MASER Engineering
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2010

Focused Ion Beam (FIB) circuit edit (CE) has been playing a pivotal role in providing insight to ramp-up yield. Numerous IC fabrication processes inherently pose unique challenges to FIB circuit edit approaches. Copper (Cu) has been the material of choice for interconnects as technology features shrink to the 180 nm node and below. Thick copper planes are used for multiple reasons that are mentioned later. Milling through thick copper planes has been tremendously challenging and time consuming during FIB circuit edits. Proposed is a methodology to enhance the bulk Cu removal process at astounding etching rates while maintaining planarity. Copyright © 2010 ASM International® All rights reserved.

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