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Ohzone T.,Dawn Enterprise Co. | Matsuda T.,Toyama Prefectural University | Fukuoka R.,Toyama Prefectural University | Hattori F.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University
Japanese Journal of Applied Physics | Year: 2016

Blue/pink/purple electroluminescence (EL) from metal-oxide-semiconductor (MOS) devices with an indium tin oxide (ITO)/[Gd/(Ta + Gd/Pr)/(Pr + Ce)-Si-O] insulator layer/n+-Si substrate surface is reported. The insulator layers were fabricated from organic liquid sources of Gd or (Ta + Gd/Pr)/(Pr + Ce) mixtures, which were spin-coated on the n+-Si substrate and annealed at 950 °C for 30min in air. The EL emission could be observed by the naked eye in the dark in the Fowler-Nordheim (FN) tunnel current regions. Peak wavelengths in the measured EL spectra were independent of the positive current. The EL intensity ratio of ultraviolet (UV) to the visible range varied with the composition ratio of the (Ta + Gd) liquids, and an optimum Ta to Gd ratio existed for the strongest blue emission, which could be attributed to the Ta-related oxide/silicate. The pink EL of the device fabricated with the (Ta : Pr = 6 : 4) mixture ratio can be explained by EL emission peaks related to the Pr3+ ions. The purple EL observed from the (Pr : Ce = 6 : 4) device corresponds to the strong and broad emission profile near the 357nm peak, which cannot be assigned to Ce3+ ions. The results suggest that the EL can be attributed to the double-layer oxides with different compositions in the MOS devices. The upper layer consists of various Ta-, Gd-, Pr-, and Ce-related oxides and their silicates, while the lower SiOx-rich layer contributes to the FN current due to the high electric field, and thus the various EL colors. © 2016 The Japan Society of Applied Physics.


Yamada K.,Toyama Prefectural University | Matsuda T.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University | Hatakeyama T.,Toyama Prefectural University | And 2 more authors.
2014 International Conference on Electronics Packaging, ICEP 2014 | Year: 2014

Temperature distributions in three dimensional (3D) ICs were analyzed with a thermal simulation and compared with measured results of test 3D ICs, in which sensor p-n diode arrays and on chip heaters were embedded. The 3D IC consists of a top tier test chip and a 410 um thick bottom dummy chip. Both top tier chips and bottom dummy chips were fabricated by a standard 0.18 um CMOS process. The top tier chips had four kinds of the thickness of 50 through 410 um. The temperature distributions of the top tier test chip under the constant heater power were analyzed by both measurements and thermal simulations. The thinner top tier structures showed the higher temperature and affected the temperature distributions. Effect of various boundary conditions such as substrate size and peripheral bonding pads were examined with thermal simulation. The test structure and the simulation modeling can provide an effective way for analysis of thermal conduction in 3D ICs. © 2014 JIEP.


Matsuda T.,Toyama Prefectural University | Yamada K.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University | Hatakeyama T.,Toyama Prefectural University | And 2 more authors.
IEEE International Conference on Microelectronic Test Structures | Year: 2014

A test structure for analysis of temperature distribution in stacked IC, which has a top tier chip attached on a bottom dummy chip with adhesive layer, is presented. The devices with four kinds of thickness of 50-410 um were fabricated. Dependences of the temperature on distance from the heater resistor were analyzed with on-chip sensor arrays, as well as fast transient phenomena. The thinner top tier structures showed the higher temperature and affected the temperature distributions. The test structure can provide an effective way for analysis of thermal properties in various LSIs. © 2014 IEEE.


Matsuda T.,Toyama Prefectural University | Matsumura Y.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University | Ohzone T.,Dawn Enterprise
IEEE International Conference on Microelectronic Test Structures | Year: 2010

Orientation dependence and asymmetry of VT (threshold voltage), gm (transconductance), S (subthreshold slope), and Ioff (off-state current at VG = 0 V) in 0.18 μm n-MOSFETs were measured and analyzed. The test structure contains 8 different channel orientation angles of 0° /45° /90° and three kinds of process conditions. Although VT, gm and S scarcely show particular anisotropy except for the variation of MOSFET structure and/or impurity profile, the orientation dependence of GIDL characteristics is observed in the wafer with the higher extension dose. ©2010 IEEE.


Ohzone T.,Dawn Enterprise Co. | Matsuda T.,Toyama Prefectural University | Hase S.,Toyama Prefectural University | Nohara S.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University
Japanese Journal of Applied Physics | Year: 2010

Current-voltage (IG-VG) and electroluminescence (EL) characteristics are reported for indium-tin oxide (ITO)/Tb-Si-O layer/n +-Si metal-oxide-semiconductor (MOS) devices. The Tb-Si-O layer was fabricated from a Tb organic compound film, which was spin-coated on an n +-Si substrate and annealed with temperatures from 700 to 1000 °C for 30 min in air. The EL intensity increased proportionally to the supply current, and it also increased with annealing temperature at the same current. The EL device emitted green light with four photon energy peaks at 2.52 eV (492 nm), 2.27 eV (547 nm), 2.11 eV (589 nm), and 1.99 eV (623 nm), which originated from the intrashell transitions of 5D4-7F J (J = 6, 5, 4, and 3) of Tb3+ ions excited by hot electrons. The surface layers on the Si substrate have a total thickness of about 30 nm and consist of a Tb2O3 layer, and a mixture layer of Tb2O3 and Tb-Si-O depending on the annealing temperature © 2010 The Japan Society of Applied Physics.


Ohzone T.,Dawn Enterprise Co. | Matsuda T.,Toyama Prefectural University | Saito S.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University
Japanese Journal of Applied Physics | Year: 2014

Ultraviolet (UV) and white electroluminescence (EL) from metal-oxide-semiconductor (MOS) devices with indium-tin oxide (ITO)/[(Gd/(Gd + Dy/ La/Ca/Ba)-Si-O] insulator layers/n+-Si substrate are reported. The insulator layers were fabricated from mixtures of organic liquid sources of (Gd) or [Gd+(Dy/La/Ca/Ba)], which were spin-coated on the n+-Si substrate and annealed at 950 ° for 30 min in air. The current IG under EL emission corresponded to the Fowler-Nordheim (FN) tunnel current. The EL intensity increased proportionally to IG to the n-th power, where n was about 1.2, and the EL spectra were independent of IG. The MOS device with the [(Gd + Dy)-Si-O] layer had the weakest EL in the UV range among the measured devices, while it had the strongest EL in the visible wavelength range. The UV and visible range EL originated from the intrashell transitions of 6P7/2- 8S7/2 in Gd3+ and 4F 9/2-6HJ/2 (J = 9, 11, 13, and 15) in Dy 3+, respectively. The devices with [(Gd/(Gd + La/Ca/Ba)- Si-O] layers emitted strong UV EL, which originated from the intrashell transitions of 6P7/2-8S7/2 in Gd3+, and had the moderate intensity of EL in the visible range. The insulator layers of EL devices had a thickness of 25-30nm and the double layer structure, whose top surface layer contained [Gd2O3+DyOx+(Gd + Dy)-Si-O]/[Gd2O3+La2O3/CaO/BaO+(Gd + La/Ca/Ba)-Si-O] silicate, while the underlayer was composed of SiOx-rich oxide with various rare earth and alkaline earth oxides.© 2014 The Japan Society of Applied Physics.


Matsuda T.,Toyama Prefectural University | Demachi H.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University | Hatakeyama T.,Toyama Prefectural University | Ohzone T.,Dawn Enterprise
IEEE International Conference on Microelectronic Test Structures | Year: 2016

A test structure for analysis of temperature distributions and effects of metal wires on thermal properties in stacked IC is presented. The effects on the temperature distributions and transient phenomena in the single die and the stacked ICs were analyzed. The heat transfer in the metal wires affects the temperature distributions, which are consistent with the thermal simulation results. The test structure can provide an effective way for analysis of thermal properties in various LSIs. © 2016 IEEE.


Matsuda T.,Toyama Prefectural University | Ichihashi K.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University | Ohzone T.,Dawn Enterprise
IEEE International Conference on Microelectronic Test Structures | Year: 2015

A test structure for reliability analysis of MOSFETs in CMOS inverters under DC and high frequency AC stress has been presented. It has an input pulse generation block with a ring oscillator, monitor inverter blocks and Kelvin connected selector switches. Detailed I - V characteristics of MOSFETs in the monitor inverters were measured and the degradation by HCI and BTI in nMOS and pMOS devices were analyzed. The dominant degradation origins in nMOS and pMOS devices can be attributed to HCI and NBTI, respectively. © 2015 IEEE.


Matsuda T.,Toyama Prefectural University | Hanai H.,Toyama Prefectural University | Tohjo T.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University | And 4 more authors.
IEEE Transactions on Semiconductor Manufacturing | Year: 2014

A test structure for analysis of temperature distribution in CMOS LSI is presented. Fundamental thermal properties of LSI chip have been measured and discussed with simulation results. The test structure consists of 24 sensor blocks, each of which has a resistor as an on-chip heater, a p-n diode or n-MOSFET array for temperature sensing and selector switches. Dependence of heating time and distance from the resistor are analyzed as well as transient phenomena. Temperature T decreases with the distance L , is proportional to the reciprocal of L~(1/L) , and empirical equations have been proposed. The results of both p-n diode and n-MOSFET sensors are nearly the same. A thermal simulation gives an L dependence of T similar to the measured result. T of 160 pin QFP becomes lower than that of 80 pin due to its larger outline, but L dependence of T is similar. The abrupt and gradual change of T at the heater switching suggests both fast and slow processes in thermal conduction. The test structure can provide an effective methodology for analysis of fundamental thermal properties in LSIs packaged in various ways. © 1988-2012 IEEE.


Matsuda T.,Toyama Prefectural University | Hanai H.,Toyama Prefectural University | Iwata H.,Toyama Prefectural University | Kondo D.,Toyama Prefectural University | And 3 more authors.
IEEE International Conference on Microelectronic Test Structures | Year: 2013

A test structure for analysis of temperature distribution in CMOS LSI is presented. Fundamental thermal properties of LSI chip were measured and discussed with simulation results. The test structure consists of 24 sensor blocks, each of which has a resistor as an on-chip heater, a p-n diode array for temperature sensing and selector switches. Dependence of heating time and distance from the resistor were analyzed as well as transient phenomena. The test structure can provide an effective methodology for analysis of fundamental thermal properties in LSIs packaged in various ways. © 2013 IEEE.

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