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Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2009.3.9 | Award Amount: 15.49M | Year: 2010

Best-Reliable Ambient Intelligent Nanosensor Systems e-BRAINS represent a giant leap for outstanding future applications in the area of ambient living with the ultimate need for integration of heterogeneous technologies, high-performance nanosensor devices, miniaturization, smart wireless communication and best-reliability.\ne-BRAINS with minimum volume and weight as well as reduced power consumption can be utilized in ambient living systems. Successful market entry of such innovative ambient intelligence products will be determined by the performance improvement achieved and the cost advantage in relation to the total system cost.\nThe basic requirement for robustness and reliability of the heterogeneous integration technologies and the nanosensor layers is in the focus of all e-BRAINS developments.\nThe designated nanosensor systems represent a very promising innovative approach with the potential to enable high-performance and precise functions in new products. The application of nanotechnology will allow large improvements in functionality and will open a wide range of applications for European companies.\nFuture e-BRAINS applications require significantly higher integration densities. Performance, multi-functionality and reliability of such complex heterogeneous systems will be limited mainly by the wiring between the subsystems. Suitable 3D integration technologies create a basis to overcome these drawbacks with the benefit of enabling minimal interconnection lengths. In addition to enabling high integration densities, 3D integration is a very promising cost-effective approach for the realization of heterogeneous systems.\nBesides the heterogeneous system integration the main criteria of e-BRAINS is the need for miniaturized energy storage/delivery systems, low power consumption, smart communication and methodology for reliability and robustness.\ne-BRAINS benefits from the established European 3D technology platform as major result of the IP e-CUBES.


Brandstatter S.,IEEE - Institute of Electrical and Electronics Engineers | Brandstatter S.,Danube Mobile Communications Engineering GmbH | Huemer M.,IEEE - Institute of Electrical and Electronics Engineers | Huemer M.,Johannes Kepler University
IEEE Access | Year: 2014

The introduction of new mobile communication standards, enabling the ever growing amount of data transmitted in mobile communication networks, continuously increases the complexity of control processing within radio frequency (RF) transceivers. Since this complexity cannot be handled by traditional approaches, this paper focuses on the partitioning of RF transceiver systems and on the implementation of application-specific components to introduce an advanced multiprocessor system-on-chip interface and control architecture which is able to fulfill the requirements of future RF transceiver integrations. The proposed framework demonstrates a high degree of scalability, flexibility, and reusability. Consequently, the time to market for products can be reduced and fast adaptations to the requirements of the market are feasible. In addition, the developed application-specific components achieve improved or at least equivalent performance results compared with common architectures while the silicon area can be reduced. This characteristic has positive effects on the costs as well as on the power consumption of the RF transceiver. © 2014 IEEE.


Broussev S.S.,Tampere University of Technology | Broussev S.S.,Danube Mobile Communications Engineering GmbH | Tchamov N.T.,Tampere University of Technology
IEEE Transactions on Circuits and Systems II: Express Briefs | Year: 2013

This paper proposes a two-phase self-assisted zero-voltage switching (ZVS) converter suitable for fully monolithic implementation. The proposed topology utilizes an auxiliary inductor connected between the two branches of a two-phase converter to achieve ZVS conditions. The proposed converter helps reduce the output voltage ripples of the standard ZVS topology. Furthermore, the auxiliary inductor could be magnetically coupled with the filtering inductor to reduce the occupied silicon area. The advantages of the proposed converter are validated through simulations on a 65-nm CMOS process. © 2004-2012 IEEE.


Magnelli L.,Danube Mobile Communications Engineering GmbH | Amoroso F.A.,University of Pisa | Crupi F.,University of Pisa | Cappuccino G.,University of Pisa | Iannaccone G.,University of Calabria
International Journal of Circuit Theory and Applications | Year: 2013

This work focuses on the subthreshold design of ultra low-voltage low-power operational amplifiers. A well-defined procedure for the systematic design of subthreshold operational amplifiers (op-amps) is introduced. The design of a 0.5-V two-stage Miller-compensated amplifier fabricated with a 0.18-μm complementary metal-oxide-semiconductor process is presented. The op-amp operates with all transistors in subthreshold region and achieves a DC gain of 70dB and a gain-bandwidth product of 18kHz, dissipating just 75nW. The active area of the chip is ≈0.057mm2. Experimental results demonstrate that well-designed subthreshold op-amps are a very attractive solution to implement sub-1-V energy-efficient applications for modern portable electronic systems. A comparative analysis with low-voltage, low-power op-amp designs available in the literature highlights that subthreshold op-amps designed according to the proposed design procedure achieve a better trade-off among speed, power, and load capacitance. © 2012 John Wiley & Sons, Ltd.


Pachler W.,University of Graz | Pressel K.,Infineon Technologies | Grosinger J.,University of Graz | Beer G.,Infineon Technologies | And 4 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2014

We present a novel three-dimensional (3D) embedded wafer-level ball grid array (eWLB) system in package (SiP) solution for biochips and micro labs. This 3D SiP includes three major components, a complementary metal oxide semiconductor (CMOS)-tunnel magneto resistance (TMR) sensor biochip for magnetic bead-sensing stacked on a radio frequency identification (RFID) microchip and a 13.56 MHz coil antenna for wireless energy and data transfer. The power supply and the serial peripheral interface (SPI) chip interconnections between the CMOS-TMR sensor biochip (slave) and the RFID microchip (master) are implemented with a novel embedded Z-line (EZL) vertical contact technology through the mold compound. The 13.56 MHz antenna is embedded into the fan-out area of the bottom redistribution layer of the eWLB. With this setup we are able to maximize the RFID reading distance and to ensure a displacement to the TMR sensor surface. We achieve an overall volume of the 3D SiP of only 5.6 mm × 3.6 mm × 0.7 mm applying the eWLB technology. Due to the RFID technology the developed 3D SiP does not need any external contacts and cabling. Therefore it can be encapsulated into harsh environments. In addition the top fan-out surface of the eWLB can be used for adhesive bonding to higher level analyzing setups. The results demonstrate that innovative SiP technology using the eWLB technology combined with chip and antenna design allow to realize modern subsystems e.g. for medical applications. © 2014 IEEE.


Magnelli L.,Danube Mobile Communications Engineering GmbH | Crupi F.,University of Calabria | Corsonello P.,University of Calabria | Iannaccone G.,University of Pisa
International Journal of Circuit Theory and Applications | Year: 2015

We present the design of a nanopower sub-threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 μm CMOS technology. The circuit provides a temperature-compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start-up circuit. © 2013 John Wiley & Sons, Ltd.


Gebhard A.,Johannes Kepler University | Kanumalli R.S.,Danube Mobile Communications Engineering GmbH | Neurauter B.,Danube Mobile Communications Engineering GmbH | Huemer M.,Johannes Kepler University
Proceedings of the IEEE Sensor Array and Multichannel Signal Processing Workshop | Year: 2016

Modern frequency division duplex radio frequency transceivers experience transmitter-to-receiver leakage due to the limited isolation of the duplexer. In Long Term Evolution-Advanced (LTE-A) carrier aggregation receivers the coupling between the local oscillators creates harmonics on the chip which can lead to the downconversion of this leakage signal to the receive (Rx) baseband. Thereby, this so-called modulated spur interference reduces the signal-to-noise ratio of the Rx signal. In this paper, the modulated spur interference is modeled and several adaptive algorithms are compared regarding their convergence and cancelation performance. To maximize the data throughput, the adaptive filter is required to converge within the short time period of one orthogonal frequency-division multiplexing (OFDM) symbol. Out of the investigated concepts the proposed variable step-size least-mean-square algorithm turns out to be the most favorable choice. It satisfies the required constraints of convergence time and cancelation performance, and it features a reasonable low complexity. © 2016 IEEE.


Ossmann P.,Johannes Kepler University | Fuhrmann J.,Friedrich - Alexander - University, Erlangen - Nuremberg | Fuhrmann J.,Danube Mobile Communications Engineering GmbH | Dufrene K.,Danube Mobile Communications Engineering GmbH | And 5 more authors.
IEEE Transactions on Microwave Theory and Techniques | Year: 2016

We present a linear two-stage power amplifier (PA) for UMTS terrestrial radio access (UTRA) applications. The PA has been designed using a standard 28-nm complementary metal-oxide-semiconductor process. It includes an on-chip input matching network, a predriver stage, and an on-chip output matching network. Additional process-voltageerature compensation circuits and electrostatic discharge protection have been implemented on-chip. A differential triple-stack transistor array acts as transconductance circuit and generates watt-level RF output power. Measured saturated output power is more than 31 dBm and peak power-added efficiency is 33% for sinusoidal operation at 1.8 GHz. When applying memoryless digital predistortion (DPD) for 3rd Generation Partnership Project (3GPP) UTRA test vectors, an adjacent-channel leakage ratio of ≤-33 dBc at ±5 MHz for 26.5-dBm output power is achieved. A corresponding error-vector magnitude of ≤1.7% can be measured when using memoryless DPD. © 2015 IEEE.


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2009.1.1 | Award Amount: 5.90M | Year: 2010

As highlighted in the Work Programme, energy efficiency and flexibility in the use of spectrum resources are two major research challenges for the development of future wireless communications technologies.\n\nTo address these challenges, SACRA project proposes to develop a multi-band cognitive radio technology. In SACRA, new techniques for the global efficiency of wireless systems will be developed in the following four directions:\n- the spectral efficiency thanks to the use of cognitive radio techniques in a multi-band scheme,\n- the minimization of electronic component number in wireless systems,\n- the energy optimization for wireless communication terminals by optimizing architecture design and algorithms implementation,\n- the minimization of the generated interference in the environment by selecting the adequate band which will guarantee the shortest transmission distance and the minimum power while preserving the QoS.\n\nThe innovation and impact brought by SACRA project are in the combination of innovative approaches on Radio Frequency (RF) front-end and base band components design with new cognitive radio techniques integrated into a demonstrator platform. The major outcome of SACRA project is a proof-of-concept able to communicate jointly and cognitively in two separate frequency bands, which corresponds to concrete needs today in Europe. The initial target scenario is the management and optimal distribution of broadband mobile communications on two separate frequency bands at 790-862 MHz and 2.6 GHz as proposed by European regulation authorities.\n\nConsidering the current ICT challenges, SACRA project, by designing and validating new techniques for spectrum and energy efficiency in wireless communications, is expected to have a significant impact on future wireless mobile systems.


Tertinek S.,Danube Mobile Communications Engineering GmbH | Feely O.,University College Dublin
IEEE Transactions on Circuits and Systems II: Express Briefs | Year: 2011

Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white phase noise) in second-order DBBPLLs, comparing the output jitter with that of first-order DBBPLLs. For small clock jitter, the nonlinear loop behavior is modeled as a 2-D Markov chain, and the output jitter is smaller than but close to that of a first-order loop. For large clock jitter, the BPD nonlinearity is linearized, and the output jitter is larger than that of a first-order loop; it is proportional to the clock jitter and inversely proportional to the square root of the stability factorthe ratio of the proportional-path gain to the integral-path gain of the digital loop filter. © 2011 IEEE.

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