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Magnelli L.,Danube Mobile Communications Engineering GmbH | Amoroso F.A.,University of Pisa | Crupi F.,University of Pisa | Cappuccino G.,University of Pisa | Iannaccone G.,University of Calabria
International Journal of Circuit Theory and Applications | Year: 2013

This work focuses on the subthreshold design of ultra low-voltage low-power operational amplifiers. A well-defined procedure for the systematic design of subthreshold operational amplifiers (op-amps) is introduced. The design of a 0.5-V two-stage Miller-compensated amplifier fabricated with a 0.18-μm complementary metal-oxide-semiconductor process is presented. The op-amp operates with all transistors in subthreshold region and achieves a DC gain of 70dB and a gain-bandwidth product of 18kHz, dissipating just 75nW. The active area of the chip is ≈0.057mm2. Experimental results demonstrate that well-designed subthreshold op-amps are a very attractive solution to implement sub-1-V energy-efficient applications for modern portable electronic systems. A comparative analysis with low-voltage, low-power op-amp designs available in the literature highlights that subthreshold op-amps designed according to the proposed design procedure achieve a better trade-off among speed, power, and load capacitance. © 2012 John Wiley & Sons, Ltd. Source

Broussev S.S.,Tampere University of Technology | Broussev S.S.,Danube Mobile Communications Engineering GmbH | Tchamov N.T.,Tampere University of Technology
IEEE Transactions on Circuits and Systems II: Express Briefs | Year: 2013

This paper proposes a two-phase self-assisted zero-voltage switching (ZVS) converter suitable for fully monolithic implementation. The proposed topology utilizes an auxiliary inductor connected between the two branches of a two-phase converter to achieve ZVS conditions. The proposed converter helps reduce the output voltage ripples of the standard ZVS topology. Furthermore, the auxiliary inductor could be magnetically coupled with the filtering inductor to reduce the occupied silicon area. The advantages of the proposed converter are validated through simulations on a 65-nm CMOS process. © 2004-2012 IEEE. Source

Brandstatter S.,IEEE - Institute of Electrical and Electronics Engineers | Brandstatter S.,Danube Mobile Communications Engineering GmbH | Huemer M.,IEEE - Institute of Electrical and Electronics Engineers | Huemer M.,Johannes Kepler University
IEEE Access | Year: 2014

The introduction of new mobile communication standards, enabling the ever growing amount of data transmitted in mobile communication networks, continuously increases the complexity of control processing within radio frequency (RF) transceivers. Since this complexity cannot be handled by traditional approaches, this paper focuses on the partitioning of RF transceiver systems and on the implementation of application-specific components to introduce an advanced multiprocessor system-on-chip interface and control architecture which is able to fulfill the requirements of future RF transceiver integrations. The proposed framework demonstrates a high degree of scalability, flexibility, and reusability. Consequently, the time to market for products can be reduced and fast adaptations to the requirements of the market are feasible. In addition, the developed application-specific components achieve improved or at least equivalent performance results compared with common architectures while the silicon area can be reduced. This characteristic has positive effects on the costs as well as on the power consumption of the RF transceiver. © 2014 IEEE. Source

Pachler W.,University of Graz | Pressel K.,Infineon Technologies | Grosinger J.,University of Graz | Beer G.,Infineon Technologies | And 4 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2014

We present a novel three-dimensional (3D) embedded wafer-level ball grid array (eWLB) system in package (SiP) solution for biochips and micro labs. This 3D SiP includes three major components, a complementary metal oxide semiconductor (CMOS)-tunnel magneto resistance (TMR) sensor biochip for magnetic bead-sensing stacked on a radio frequency identification (RFID) microchip and a 13.56 MHz coil antenna for wireless energy and data transfer. The power supply and the serial peripheral interface (SPI) chip interconnections between the CMOS-TMR sensor biochip (slave) and the RFID microchip (master) are implemented with a novel embedded Z-line (EZL) vertical contact technology through the mold compound. The 13.56 MHz antenna is embedded into the fan-out area of the bottom redistribution layer of the eWLB. With this setup we are able to maximize the RFID reading distance and to ensure a displacement to the TMR sensor surface. We achieve an overall volume of the 3D SiP of only 5.6 mm × 3.6 mm × 0.7 mm applying the eWLB technology. Due to the RFID technology the developed 3D SiP does not need any external contacts and cabling. Therefore it can be encapsulated into harsh environments. In addition the top fan-out surface of the eWLB can be used for adhesive bonding to higher level analyzing setups. The results demonstrate that innovative SiP technology using the eWLB technology combined with chip and antenna design allow to realize modern subsystems e.g. for medical applications. © 2014 IEEE. Source

Magnelli L.,Danube Mobile Communications Engineering GmbH | Crupi F.,University of Calabria | Corsonello P.,University of Calabria | Iannaccone G.,University of Pisa
International Journal of Circuit Theory and Applications | Year: 2015

We present the design of a nanopower sub-threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 μm CMOS technology. The circuit provides a temperature-compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start-up circuit. © 2013 John Wiley & Sons, Ltd. Source

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