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Quay R.,Fraunhofer Institute for Applied Solid State Physics | Waltereit P.,Fraunhofer Institute for Applied Solid State Physics | Kuhn J.,Fraunhofer Institute for Applied Solid State Physics | Bruckner P.,Fraunhofer Institute for Applied Solid State Physics | And 4 more authors.
IEEE MTT-S International Microwave Symposium Digest | Year: 2013

This paper reports on two AlGaN/GaN MMIC technologies, performances of MMICs and modules, and reliability for space applications at X-band to W-band frequencies. Quarter-micron gate length HEMTs deliver 5 W/mm output power density at 30 V drain bias with >58% PAE at 10 GHz operating frequency. Dual-stage 8 W output power MMICs for telemetry applications in space have a PAE of more than 50% at 8.5 GHz with a lifetime of 106 h at a channel temperature of 200°C. Space evaluation tests indicate a stability of this technology suitable for space. For scientific missions a high-gain high power amplifier MMIC and module have been developed for 90 GHz operation with up to 16 dB of linear gain and 400 mW of output power. © 2013 IEEE. Source


Diebold S.,Osaka University | Kuhn J.,Fraunhofer Institute for Applied Solid State Physics | Hulsmann A.,Fraunhofer Institute for Applied Solid State Physics | Leuther A.,Fraunhofer Institute for Applied Solid State Physics | And 6 more authors.
2014 Asia-Pacific Microwave Conference Proceedings, APMC 2014 | Year: 2014

For radiometric application in the frequency range around 325 GHz, two low noise amplifier millimeter-wave monolithic integrated circuits have been developed. They use metamorphic high electron mobility transistors with a gate-length of 35 nm. The first amplifier only uses transistors in common-source configuration, whereas the second only employs transistors in cascode configuration. Their simulated and measured performance is compared to find which configuration is advantageous for the design of low noise amplifiers in this frequency range. Copyright 2014 IEICE. Source


Niaki S.H.A.,KTH Royal Institute of Technology | Beserra G.S.,University of Brasilia | Andersen N.,Novelda AS | Verdon M.,DA Design Oy | Sander I.,KTH Royal Institute of Technology
Proceedings - SBCCI 2012: 25th Symposium on Integrated Circuits and Systems Design | Year: 2012

The design of today's electronic embedded systems is an increasingly complicated task. This is especially problematic for Small and Medium Enterprises (SMEs) which have limited resources. In this work, we identify a set of common design practices used in industry, with a special focus on problems faced by smaller companies, and formulate them as design scenarios. We show how SMEs can benefit from a system-level design approach by customizing a formal heterogeneous system modeling framework for each scenario. The applicability of this approach is demonstrated by two industrial use cases, an impulse-radio radar and a UART-based protocol. ©2012 IEEE. Source


Niaki S.H.A.,KTH Royal Institute of Technology | Jakobsen M.K.,Technical University of Denmark | Sulonen T.,DA Design Oy | Sander I.,KTH Royal Institute of Technology
Forum on Specification and Design Languages | Year: 2012

Electronic System Level (ESL) design of embedded systems proposes raising the abstraction level of the design entry to cope with the increasing complexity of such systems. To exploit the benefits of ESL, design languages should allow specification of models which are a) heterogeneous, to describe different aspects of systems; b) formally defined, for application of analysis and synthesis methods; c) executable, to enable early detection of specification; and d) parallel, to exploit the multi- and many-core platforms for simulation and implementation. We present a modeling library on top of SystemC, targeting heterogeneous embedded system design, based on four models of computation. The library has a formal basis where all elements are well defined and lead in construction of analyzable models. The semantics of communication and computation are implemented by the library, which allows the designer to focus on specifying the pure functional aspects. A key advantage is that the formalism is used to export the structure and behavior of the models via introspection as an abstract representation for further analysis and synthesis. © 2012 ECSI. Source


Abu Bakar F.,Aalto University | Holmberg J.,VTT Technical Research Center of Finland | Nieminen T.,Aalto University | Nehal Q.,Aalto University | And 5 more authors.
2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 | Year: 2012

An integrated receiver consisting of RF front ends, analog baseband chain with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm2. The RF front end consists of three parallel signal channels intended for L,C and X-band of the SAR receiver. The baseband (BB) is selectable between 50 MHz and 160 MHz bandwidths through switches. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 dB and 37 dB and noise figure of 11 dB and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz baseband and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz baseband and 8 bit mode ADC. © 2012 IEEE. Source

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