San Jose, CA, United States
San Jose, CA, United States

Cypress Semiconductor Corporation is a Silicon Valley-based semiconductor design and manufacturing company founded by T. J. Rodgers and others from Advanced Micro Devices. It was formed in 1982 with backing by Sevin Rosen and went public in 1986. The company initially focused on the design and development of high speed CMOS SRAMs, EEPROMs, PAL devices, and TTL logic devices. Two years after going public the company switched from the NASDAQ to the New York Stock Exchange. In October 2009, the company announced it would switch its listing to the NASDAQ on November 12, 2009. Its headquarters are in San Jose, California, and it has divisions in the United States, Ireland, India and the Philippines as well as a fabrication plant in Minnesota.Some of its main competitors include Microchip Technology, Integrated Device Technology, Samsung Electronics, and Xilinx. Wikipedia.


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Patent
Cypress Semiconductor | Date: 2016-09-30

A radio frequency identification (RFID) integrated circuit includes a transceiver and a processing device. The transceiver may to transmit a first continuous wave radio frequency (RF) signal to a bridge in a no-wire format via an antenna, where the transceiver is to start transmitting the modulated or continuous wave RF signal at a first amplitude value and increase an amplitude of the modulated or continuous wave RF signal to a second amplitude value at which an acknowledge (ACK) pulse is detected. The transceiver may receive a reflected wave RF signal in the no-wire format. The processing device may detect the ACK pulse in the reflected wave RF signal. The processing device may transmit a second modulated or continuous wave RF signal to the transceiver in the no-wire format.


Patent
Cypress Semiconductor | Date: 2016-10-10

A protecting circuit includes: a discharge switch configured to connect to a first terminal and a second terminal; a trigger circuit comprising load devices configured to be connected in series between the first terminal and the second terminal, each of the load devices being configured to consume power; and a shunt circuit comprising, between the trigger circuit and the first terminal or the second terminal, at least one shunt pathway configured to be capable of bypassing at least one of the load devices. The trigger circuit is configured to turn on the discharge switch when a voltage between the first terminal and the second terminal is higher than a first voltage value, and the shunt circuit is configured to electrically connect the shunt pathway when the voltage is higher than a second voltage value that is greater than the first voltage value.


Patent
Cypress Semiconductor | Date: 2016-09-16

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.


Patent
Cypress Semiconductor, Ramkumar, Jin and Jenne | Date: 2017-05-10

Disclosed is a method comprising: forming above a surface on a substrate a stack of gate layers including at least two gate layers separated by at least one dielectric layer; forming a non-volatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; forming on sidewalls of the first opening a charge-trapping layer; and forming on inside sidewalls of the charge-trapping layer a thin layer of semiconducting material, and substantially filling the first opening with a dielectric material separated from the stack of gate layers by the thin layer of semiconducting material the charge-trapping layer; and forming a MOS devices in a second region of the stack of gate layers.


Patent
Cypress Semiconductor | Date: 2016-11-09

A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint sensor-compatible overlay are also disclosed.


Patent
Cypress Semiconductor | Date: 2016-03-31

A circuit, system, and method for measuring capacitance are described. A current may be received at an input of a conversion circuit. The current may be converted to a voltage signal which may be used to create a negative feedback current to the input of the conversion circuit and which may be demodulated digitally to provide a static digital output representative of a capacitance.


Patent
Cypress Semiconductor | Date: 2016-09-29

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.


Patent
Cypress Semiconductor | Date: 2016-12-05

A sensor-compatible overlay is disclosed which uses anisotropic conductive material to increase capacitive coupling of a conductive object through the overlay material to a capacitive sensor. The anisotropic conductive material has increased conductivity in a direction orthogonal to the capacitive sensor. In one embodiment, the overlay is configured to enclose a device which includes a capacitive sensor. In another embodiment, the overlay is configured as a glove.


Maheshwari D.,Cypress Semiconductor
Digest of Technical Papers - IEEE International Solid-State Circuits Conference | Year: 2014

Networking relies on fast line card packet rates that are directly proportional to and limited by the Random Transaction Rate (RTR) of the memory system. Networking line cards to date are ≤200Gb/s and were able to use memories optimized for latency (SRAM) and bandwidth (SDRAM) designed for computing systems. Next generation line cards are ≥400Gb/s and the memory system for these line cards need to be explicitly architected and designed for delivering the required high RTR. © 2014 IEEE.


Patent
Cypress Semiconductor | Date: 2016-09-07

A capacitive sensor includes a switching capacitor circuit, a comparator, and a charge dissipation circuit. The switching capacitor circuit reciprocally couples a sensing capacitor in series with a modulation capacitor during a first switching phase and discharges the sensing capacitor during a second switching phase. The comparator is coupled to compare a voltage potential on the modulation capacitor to a reference and to generate a modulation signal in response. The charge dissipation circuit is coupled to the modulation capacitor to selectively discharge the modulation capacitor in response to the modulation signal.

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