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Romero-Aguirre E.,CIVESTAV GDL | Carrasco-Alvarez R.,UDG CUCEI | Parra-Michel R.,CIVESTAV GDL | Orozco-Lugo A.G.,CINVESTAV | Mondragon-Torres A.F.,Rochester Institute of Technology
Journal of Signal Processing Systems | Year: 2013

Channel estimation based on superimposed training (ST) has been an active research topic around the world in recent years, because it offers similar performance when compared to methods based on pilot assisted transmissions (PAT), with the advantage of a better bandwidth utilization. However, physical implementations of such estimators are still under research, and only few approaches have been reported to date. This is due to the computational burden and complexity involved in the algorithms in conjunction with their relative novelty. In order to determine the suitability of the ST-based channel estimation for commercial applications, the performance and complexity analysis of the ST approaches is mandatory. This work proposes two full-hardware channel estimator architectures for a data-dependent superimposed training (DDST) receiver with perfect synchronization and nonexistent DC-offset. These architectures were described using Verilog HDL and targeted in Xilinx Virtex-5 XC5VLX110T FPGA. The synthesis results of such estimators showed a consumption of 3 % and 1 % of total slices available in the FPGA and frequencies operation over 160 MHz. They have also been implemented on a generic 90 nm CMOS process achieving clock frequencies of 187 MHz and 247 MHz while consuming 3.7 mW and 2.74 mW, respectively. In addition, for the first time, a novel architecture that includes channel estimation, training/block synchronization andDC-offset estimation is also proposed. Its fixed-point analysis has been carried out, allowing the design to produce practically equal performance to those achieved with the floating-point models. Finally, the high throughputs and reduced hardware consumptions of the implemented channel estimators, leads to the conclusion that ST/DDST can be utilized in practical communications systems. © Springer Science+Business Media New York 2012. Source


Santos L.C.,Autonomous University of Yucatan | Atoche A.C.,Autonomous University of Yucatan | Castilloy J.V.,University of Quintana Roo | Gandaraz O.L.,Systems and IT | And 2 more authors.
2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 | Year: 2015

Reconstructive signal processing algorithms involve complex computations, where matrix inversion is one of the most complex operations required by several signal processing applications (e.g., image processing or MIMO systems in wireless communication transmission). Currently, QR decomposition implemented with systolic arrays have been proposed in recent studies; however, the internal structure of the boundary cell requires complex operations such as square root and its reciprocal. The challenge of this paper consist in the improvement of a hardware architecture for matrix inversion. This improvement is achieved using systolic arrays and polynomial approximation techniques. Particularly, the inverse square root operation and its reciprocal are efficiently implemented with a piecewise polynomial approximation architecture in a systolic array structure achieving significant gains in area and time performance. © 2015 IEEE. Source


Romero-Aguirre E.,CINVESTAV | Parra-Michel R.,CINVESTAV | Carrasco-Alvarez R.,UDG CUCEI | Orozco-Lugo A.G.,CINVESTAV
Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 | Year: 2011

Channel estimation is a challenging problem in wireless communication systems because of users mobility and limited bandwidth. A plethora of methods based on pilot assisted transmissions (PAT) have been proposed in most practical systems to overcome this problem, but with the penalty of extra bandwidth consumption for training. Channel estimation based on superimposed training (ST) has emerged as an alternative in recent years because it saves valuable bandwidth by adding a training periodic sequence to the data signal instead of multiplexing them. However, although ST and one of its variants, known as data dependent ST (DDST), have been an active research topic, only few physical implementations of such estimators have been reported to date. In this work a full-hardware architecture based on array processors (AP) for DDST channel estimation is presented and it is compared with previous approaches. The design was described using Verilog HDL and targeted in Xilinx Virtex-5 XC5VLX110T. The synthesis results showed a slices consumption of 3% and a frequency operation of the 115 MHz. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator implemented in hardware is practically the same than the one obtained with the floating-point golden model. The high performance and reduced hardware of the proposed channel estimator allows us to conclude that it can be utilized in practical DDST receivers developments. © 2011 IEEE. Source


Romero-Aguirre E.,CINVESTAV | Parra-Michel R.,CINVESTAV | Carrasco-Alvarez R.,UDG CUCEI | Orozco-Lugo A.G.,CINVESTAV
International Journal of Reconfigurable Computing | Year: 2012

In this paper, a configurable superimposed training (ST)/data-dependent ST (DDST) transmitter and architecture based on array processors (APs) for DDST channel estimation are presented. Both architectures, designed under full-hardware paradigm, were described using Verilog HDL, targeted in Xilinx Virtex-5 and they were compared with existent approaches. The synthesis results showed a FPGA slice consumption of 1% for the transmitter and 3% for the estimator with 160 and 115 MHz operating frequencies, respectively. The signal-to-quantization-noise ratio (SQNR) performance of the transmitter is about 82 dB to support 4/16/64-QAM modulation. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator implemented in hardware is practically the same as the one obtained with the floating-point golden model. The high performance and reduced hardware of the proposed architectures lead to the conclusion that the DDST concept can be applied in current communications standards. © 2012 E. Romero-Aguirre et al. Source

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