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Wang C.,Xian University of Technology | Sun C.,CSMC Technologies Corporation
Journal of Semiconductors | Year: 2011

This paper proposes a new shallow trench and planar gate MOSFET (TPMOS) structure based on VDMOS technology, in which the shallow trench is located at the center of the n- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication. Source


Lv Y.,CAS Institute of Microelectronics | Jiang W.,CSMC Technologies Corporation | Ou W.,CSMC Technologies Corporation
IEEE Sensors Journal | Year: 2015

To improve the performance of infrared (IR) detectors, a novel air Fabry-Perot (FP) microcavity with high IR absorption has been studied. Based on the theory of FP cavity, the model of air FP microcavity has been proposed. Its materials have been selected through optical simulation and experimental verification. Then, the optical property and structural stress of the FP cavity have been simulated by finite difference time domain method and finite-element method. In the experiment, the test structure of air FP cavity is fabricated to verify the theoretical results. According to the experimental results, the IR absorption of this structure can reach to 85%. In addition, the application of the air FP microcavity can improve the performance of IR detector obviously. © 2014 IEEE. Source


Zhu J.,Nanjing Southeast University | Sun W.,Nanjing Southeast University | Zhang Y.,Nanjing Southeast University | Lu S.,Nanjing Southeast University | And 3 more authors.
IEEE Transactions on Power Electronics | Year: 2016

An integrated bootstrap diode emulator, including the high voltage field-effect-transistor (HV-FET), the gate control circuit and the back-gate control circuit, is experimentally proposed base on p-sub/p-epi bipolar-CMOS-DMOS technology for the first time. By adopting the gate and the back-gate control circuits, the charging time of the bootstrap capacitor can be improved by about 27% without any latch-up issues. The measured blocking voltage of the proposed HV-FET is higher than 750 V, which can be embedded in the isolation structure without sacrificing the chip area and is suitable for 600-V motor control system application. Finally, a 600-V-class high voltage gate drive IC with the proposed integrated bootstrap diode emulator is fabricated. The chip size is about 2.1 mm2 and the charging duration is about 80 μs with 1-μF bootstrap capacitor. © 2015 IEEE. Source


Zhu J.,Nanjing Southeast University | Sun W.,Nanjing Southeast University | Qian Q.,Nanjing Southeast University | Cao L.,Nanjing Southeast University | And 2 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2013

The tridimensional channel SOI-LIGBT on 1.5μm thin SOI layer is developed in this paper. The key feature of the device is that there are numerous separated P-body cells located in the emitter region, which can increase the efficient channel width, enhance electron injection and attain a large current capability. The proposed SOI-LIGBT exhibits the current density of 150A/cm2, which has an improvement of 150% compared with the conventional structure. The SOI-LIGBT structure can be well applied in high voltage integrated circuit (HVIC). © 2013 IEEE. Source


Sun W.,Nanjing Southeast University | Zhu J.,Nanjing Southeast University | Qian Q.,Nanjing Southeast University | Hou B.,Nanjing Southeast University | And 2 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2012

A novel double-well (DW) divided RESURF isolation structure featuring two slender N-Well regions at N --Well, aiming at improving the off-state breakdown voltage for high voltage IC (HVIC) is proposed in this paper. The N-Well regions in the presented structure efficiently prevent N --Well which used for the drift region of the Lateral Double Diffused MOSFET (LDMOS) from depleting with P-Well, so as to maintain the RESURF condition. The experiment results show that the proposed structure exhibits the breakdown voltage of 760V which has an improvement of 15% compared with the conventional structure. © 2012 IEEE. Source

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