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Ye R.,Nanjing Southeast University | Liu S.,Nanjing Southeast University | Sun W.,Nanjing Southeast University | Su W.,CSMC Technologies Corporation | And 3 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2016

In this work, a novel ESD failure mechanism for the LDMOS with low on-resistance and large geometric array used as output device is presented. A novel structure based on the failure mechanism is also proposed to improve its ESD robustness. The secondary break current (It2) of the modified LDMOS is increased by almost 50% without changing other characteristics basically. © 2016 IEEE.


Wei J.,Nanjing Southeast University | Zhang C.,Nanjing Southeast University | Liu S.,Nanjing Southeast University | Sun W.,Nanjing Southeast University | And 3 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2016

In this work, the Hot-Carrier-Induced (HCI) degradation mechanism of the 30 V shallow trench isolation (STI) n-type lateral DMOS (nLDMOS) with two-step-oxide process applied in high side application (called as HS-nLDMOS) is investigated. It implies that the Ron, sp (on-resistance measured under high side condition) suffers from more damage impact than Ron, ls (on-resistance measured under low side condition). Moreover, a shift of the worst stress condition from the maximum substrate current stress condition (Isubmax) to the maximum gate voltage stress condition (Vgmax) is observed when the HS-nLDMOS is evaluated with Ron, hs instead of Ron, ls. Hence our investigation suggests estimating the degradation of HS-nLDMOS by Ron, hs under Vgmax stress condition in order to evaluate the exact life of the device. © 2016 IEEE.


Zhu J.,Nanjing Southeast University | Sun W.,Nanjing Southeast University | Zhang Y.,Nanjing Southeast University | Lu S.,Nanjing Southeast University | And 3 more authors.
IEEE Transactions on Power Electronics | Year: 2016

An integrated bootstrap diode emulator, including the high voltage field-effect-transistor (HV-FET), the gate control circuit and the back-gate control circuit, is experimentally proposed base on p-sub/p-epi bipolar-CMOS-DMOS technology for the first time. By adopting the gate and the back-gate control circuits, the charging time of the bootstrap capacitor can be improved by about 27% without any latch-up issues. The measured blocking voltage of the proposed HV-FET is higher than 750 V, which can be embedded in the isolation structure without sacrificing the chip area and is suitable for 600-V motor control system application. Finally, a 600-V-class high voltage gate drive IC with the proposed integrated bootstrap diode emulator is fabricated. The chip size is about 2.1 mm2 and the charging duration is about 80 μs with 1-μF bootstrap capacitor. © 2015 IEEE.


Liu S.,Nanjing Southeast University | Zhang C.,Nanjing Southeast University | Sun W.,Nanjing Southeast University | Su W.,CSMC Technologies Corporation | And 3 more authors.
Applied Physics Letters | Year: 2014

Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic. © 2014 AIP Publishing LLC.


Liu S.,Nanjing Southeast University | Sun W.,Nanjing Southeast University | Wan W.,Nanjing Southeast University | Su W.,CSMC Technologies Corporation | And 2 more authors.
IEEE Electron Device Letters | Year: 2013

In this letter, the hot-carrier-induced linear drain current degradations of the n-type lateral double-diffused MOS (LDMOS) transistor under the pulse gate stress with different amplitudes and the worst dc gate stress are experimentally compared. They show that the degradation under the 1.5 V pulse gate stress is less than that under the worst dc gate stress (1.5 V). However, under the 5 V pulse gate stress, the degradation is about two times larger than that under the worst dc gate stress because of the enhanced impact ionization at the pulse falling edge. In this way, the large gate pulse amplitude stress is used for evaluating the hot-carrier-induced lifetime of the LDMOS working with the large gate pulse. © 1980-2012 IEEE.


Qian Q.,Nanjing Southeast University | Sun W.,Nanjing Southeast University | Liu S.,Nanjing Southeast University | Shi L.,Nanjing Southeast University | And 3 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2012

The linear drain current degradations of the Field Gate p-type Lateral Extended Drain MOS(FG-pLEDMOS)for different AC hot-carrier stress conditions have been experimentally investigated for the first time. It is noted that the hot-carrier degradation has closed relation with duty cycle and the degradation recovery phenomenon has been discovered in this novel device. The experimental results also show that the degradation strongly depends on the time of rising and falling edge of the gate signal pulse. The FG-pLEDMOS stressed at faster rising and falling edge will suffer from more serious hot-carrier degradation. © 2012 IEEE.


Sun W.,Nanjing Southeast University | Zhu J.,Nanjing Southeast University | Qian Q.,Nanjing Southeast University | Hou B.,Nanjing Southeast University | And 2 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2012

A novel double-well (DW) divided RESURF isolation structure featuring two slender N-Well regions at N --Well, aiming at improving the off-state breakdown voltage for high voltage IC (HVIC) is proposed in this paper. The N-Well regions in the presented structure efficiently prevent N --Well which used for the drift region of the Lateral Double Diffused MOSFET (LDMOS) from depleting with P-Well, so as to maintain the RESURF condition. The experiment results show that the proposed structure exhibits the breakdown voltage of 760V which has an improvement of 15% compared with the conventional structure. © 2012 IEEE.


Zhu J.,Nanjing Southeast University | Sun W.,Nanjing Southeast University | Qian Q.,Nanjing Southeast University | Cao L.,Nanjing Southeast University | And 2 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2013

The tridimensional channel SOI-LIGBT on 1.5μm thin SOI layer is developed in this paper. The key feature of the device is that there are numerous separated P-body cells located in the emitter region, which can increase the efficient channel width, enhance electron injection and attain a large current capability. The proposed SOI-LIGBT exhibits the current density of 150A/cm2, which has an improvement of 150% compared with the conventional structure. The SOI-LIGBT structure can be well applied in high voltage integrated circuit (HVIC). © 2013 IEEE.


Lv Y.,CAS Institute of Microelectronics | Jiang W.,CSMC Technologies Corporation | Ou W.,CSMC Technologies Corporation
IEEE Sensors Journal | Year: 2015

To improve the performance of infrared (IR) detectors, a novel air Fabry-Perot (FP) microcavity with high IR absorption has been studied. Based on the theory of FP cavity, the model of air FP microcavity has been proposed. Its materials have been selected through optical simulation and experimental verification. Then, the optical property and structural stress of the FP cavity have been simulated by finite difference time domain method and finite-element method. In the experiment, the test structure of air FP cavity is fabricated to verify the theoretical results. According to the experimental results, the IR absorption of this structure can reach to 85%. In addition, the application of the air FP microcavity can improve the performance of IR detector obviously. © 2014 IEEE.


Zhang W.,University of Electronic Science and Technology of China | Zhang W.,CSMC Technologies Corporation | Qiao M.,University of Electronic Science and Technology of China | Wu L.,Chengdu University of Information Technology | And 7 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2013

An ultra-low specific on-resistance (Ron, sp) high voltage trench SOI LDMOS based on the enhanced bulk field (ENBULF) concept is proposed. The key feature of this new device is heavily doped N/P pillars parallel to the trench oxide layer. The bulk electric field of the trench LDMOS is enhanced both in the dielectric and the silicon layer by using the N/P pillars. Firstly, the highly doped N/P pillars introduce two new electric field peaks in the bulk of the drift region, which enhances the bulk electric fields both under the drain and source. Secondly, the additional electric field of the trench oxide layer is produced by N/P pillars, leading to a shrink of the drift area. Thirdly, the enhanced dielectric layer field (ENDIF) effect of the BOX layer occurs self-adaptively with different thicknesses of the BOX layer. Combining the trench and SJ technologies, the cell pitch is reduced and the optimized doping concentration of the drift region is increased. The Ron, sp is therefore reduced efficiently. The 2-D analytical model of the ENBULF LDMOS is developed to guide the design of the novel device. Based on the model and the simulation, the ENBULF LDMOS exhibits a offstate BV of 684 V and a R on, sp of 48.5 mω·cm2. The new device breaks through the silicon limit in a wide applied voltage levels. © 2013 IEEE.

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