San Francisco, CA, United States
San Francisco, CA, United States

Cryptography Research, Inc.. is a San Francisco based cryptography company specializing in applied cryptographic engineering, including technologies for building tamper-resistant semiconductors. It was purchased on June 6, 2011 by Rambus for $342.5M. The company licenses patents for protecting cryptographic devices against power analysis attacks. The company's CryptoFirewall-brand ASIC cores are used in pay TV conditional access systems and anti-counterfeiting applications. CRI also developed BD+, a security component in the Blu-ray disc format, and played a role in the format war between HD DVD and Blu-ray. The company's services group assists with security testing, disaster recovery, and training.Cryptography Research protects its core operations from outside attack by maintaining a secured local network that is not connected to the Internet at all. Employees who need to work with sensitive data have two computers on their desks — one to access the secure network, and a separate computer to access the Internet.In 2009, Frost & Sullivan awarded the company the World Smart Card Technology Leadership of the Year Award, noting that the company is "one of the highest-volume and highest-value technology licensors in the semiconductor industry" and that "more than 4 billion security chips are produced under its licenses every year". Wikipedia.


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Patent
Cryptography Research | Date: 2015-11-23

Encrypted data transmitted from a second entity to a first entity may be received. The encrypted data may be encrypted by a location based public key based on a public key and a location associated with the second entity. A location associated with the first entity may be identified. A location based private key may be generated based on a private key that corresponds to the public key and the location associated with the first entity. Furthermore, the encrypted data may be decrypted with the location based private key when the location associated with the first entity matches the location associated with the second entity.


Patent
Cryptography Research | Date: 2016-08-24

A side-channel attack resistant circuit topology for performing logic functions. This topology includes combinatorial logic to perform the at least one logic function. A logic input selector alternately supplies, in response to a first timing reference signal, an input to the combinatorial logic with noise generating input values and valid input values. A first latch input selector alternately supplies, in response to the first timing reference signal, a first memory element input with noise generating input values and valid logic output values. The valid logic output values are received from the combinatorial logic. A first memory element latches the valid logic output values in response to a second timing reference signal.


Systems and methods for performing cryptographic data processing operations in a manner resistant to external monitoring attacks. An example method may comprise: executing, by a processing device, a first data manipulation instruction, the first data manipulation instruction affecting an internal state of the processing device; executing a second data manipulation instruction, the second data manipulation instruction interacting with said internal state; and breaking a detectable interaction of the first data manipulation instruction and the second data manipulation instruction by executing a third data manipulation instruction utilizing an unpredictable data item.


Patent
Cryptography Research | Date: 2016-05-12

A virtual memory including virtual addresses may be generated. A first virtual address of the virtual memory may be mapped to a first physical address of a one-time programmable (OTP) memory of a device. Furthermore, a second virtual address of the virtual memory may be mapped to a second physical address of a static memory of the device. The virtual memory that is mapped to the OTP memory and the static memory may be provided for accessing of the data of the OTP memory of the device.


A device includes storage hardware to store a secret value and processing hardware coupled to the storage hardware. The processing hardware is to receive an encrypted data segment with a validator and derive a decryption key using the secret value and a plurality of entropy distribution operations. The processing hardware is further to verify, using the received validator, that the encrypted data segment has not been modified. The processing hardware is further to decrypt the encrypted data segment using the decryption key to produce a decrypted data segment responsive to verifying that the encrypted data segment has not been modified.


Patent
Cryptography Research | Date: 2015-03-26

Pairing data associated with a second device may be received at a first device. The pairing data may be received from a server. A first authentication proof may be generated based on the pairing data received from the server. A second authentication proof may be received from the second device. Furthermore, an authentication status of the second device may be updated based on a comparison of the first authentication proof that is based on the pairing data received from the server and the second authentication proof that is received from the second device.


Patent
Cryptography Research | Date: 2016-07-06

A base key that is stored at a mobile device may be received. A first dynamic key that is based on the base key may be generated. First transaction data corresponding to a first transaction associated with the mobile device may be received. Furthermore, the first dynamic key may be updated to generate a second dynamic key based on a combination of the first dynamic key and the first transaction data corresponding to the first transaction. Authentication of a second transaction associated with the mobile device may be requested based on the second dynamic key.


Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.


Patent
Cryptography Research | Date: 2016-03-17

A value corresponding to an input for a cryptographic operation may be received. The value may blinded by multiplying the value based on an exponentiation of a random number raised to an exponent value that is associated with a public key. A cryptographic operation may be performed based on the blinded value.


Patent
Cryptography Research | Date: 2016-04-21

Input signals may be received. Furthermore, a control signal controlling the implementation of a Differential Power Analysis (DPA) countermeasure may be received. One of the input signals may be transmitted as an output signal based on the control signal. A cryptographic operation may be performed based on the first output signal that is transmitted based on the control signal.

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