Niigata-shi, Japan
Niigata-shi, Japan

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Takeuchi S.,Nagoya University | Takeuchi S.,Covalent Silicon Corporation | Shimura Y.,Nagoya University | Shimura Y.,Japan Society for the Promotion of Science | And 14 more authors.
Solid-State Electronics | Year: 2011

In this paper, we propose the fabrication of whole strained Ge complementary metal-oxide-semiconductor (CMOS) with Ge1- xSnx materials as stressors to outperform the state-of-the-art uniaxial compressive strained Si CMOS. Ge1- xSnx materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Firstly, we have demonstrated p-type doped Ge1-xSnx growth by using either B implantation or in situ Ga doping technique. In the B-implanted Ge1-xSnx formation case, fully strained B-doped Ge1-xSnx layers with no Sn precipitation can be obtained even after solid phase epitaxial regrowth (SPER). However, the serious dislocation generation in the layer was occurred during SPER. This is caused by the point defects introduced by B implantation. In order to avoid this crystal damage, we have also demonstrated in situ Ga-doped Ge1- xSnx growth. In this case, we can achieve fully strained Ga-doped Ge1-xSnx growth without Sn precipitation and any defect generation. Secondary, we have demonstrated the formation of Ni(Ge1-ySny) layers for metal/semiconductor contact and investigated the crystalline qualities. The formation of polycrystalline Ni(Ge1-ySny) layers on Ge1-xSnx layers with Sn contents ranging from 2.0% to 6.5% after annealing at from 350 °C to 550 °C can be achieved. Additionally, in the case of the Ni/Ge1- xSnx/Ge sample with a Sn content of 3.5%, an epitaxial Ni2(Ge1-ySny) layer on a Ge 1-xSnx layer was formed. However, the surface roughness due to the agglomeration of Ni(Ge1-xSn x) increases with increasing the Sn content and the annealing temperature. Therefore, a low thermal budget must be required for the formation of Ni(Ge1-xSnx) with high Sn content. © 2011 Elsevier Ltd. All rights reserved.


Minami T.,Covalent Materials Corporation | Minami T.,Covalent Silicon Corporation | Maeda S.,Covalent Materials Corporation | Maeda S.,Covalent Silicon Corporation | And 4 more authors.
Journal of Crystal Growth | Year: 2011

The generation mechanism of pinhole defects in the Czochralski (CZ)-grown silicon (Si) single crystals was clarified by in-situ observations of bubble formation at the interface between Si melt and a silica glass crucible in a small experimental apparatus. The nucleation and growth of bubbles were facilitated by creating small cavities on the inner wall of the crucible. Si melting was conducted in an argon (Ar) atmosphere, and the pressure was maintained at either 100 Torr or close to a vacuum (no Ar-gas flow). It was found that in the presence of Ar, bubbles formed in the cavities immediately after the cavities came in contact with the melt. However, no bubbles formed in a vacuum in the experimental apparatus. These results indicate that the bubbles formed in the cavities are largely filled with Ar, and the initial bubble volumes are nearly comparable with those of the cavities. In an initial stage of expansion of a bubble, estimated volumes changed nearly in accordance with the BoyleCharles law. Further, participation of SiO gas in bubble growth may explain the deviation of the bubble volume from the theoretical value anticipated if only Ar gas was involved in the bubble growth. © 2010 Elsevier B.V. All rights reserved.


Sakai A.,Osaka University | Yamasaka S.,Osaka University | Kikkawa J.,Osaka University | Takeuchi S.,Osaka University | And 5 more authors.
ECS Transactions | Year: 2012

Wafer bonding is an attractive process to creat new structures and materials, alternative to conventional bulk-Si substrates, in the form of substrates for the advanced metal-oxide-semiconductor field effect transistors (MOSFETs). A germanium on insulator (GOI) substrate attracts much attention because it makes the best use of the higher carrier mobility advantages compared with Si, and is suitable to further downscaling of Ge MOSFET dimensions. However, careful consideration is given especially to the bonded interface between Ge and buried oxide, which should have a device grade quality. In this work, we fabricate GOI substrates by using a wafer bonding method. Atomic structures, chemistry, and electrical properties of the Ge/BOX interface are also characterized. © The Electrochemical Society.


Ando Y.,Kyushu University | Maeda Y.,Kyushu University | Kasahara K.,Kyushu University | Yamada S.,Kyushu University | And 8 more authors.
Applied Physics Letters | Year: 2011

We demonstrate spin accumulation signals controlled by the gate voltage in a metal-oxide-semiconductor field effect transistor structure with a Si channel and a CoFe/n+-Si contact at room temperature. Under the application of a back-gate voltage, we clearly observe the three-terminal Hanle-effect curves, i.e., spin accumulation signals. The magnitude of spin accumulation signals can be reduced with increasing the gate voltage. We consider that the gate controlled spin signals are attributed to the change in the carrier density in the Si channel beneath the CoFe/n+-Si contact. This study is not only a technological jump for Si-based spintronic applications with gate structures but also reliable evidence for the spin injection into the semiconducting Si channel at room temperature. © 2011 American Institute of Physics.


Araki K.,Covalent Silicon Corporation | Maeda S.,Covalent Silicon Corporation | Senda T.,Covalent Silicon Corporation | Sudo H.,Covalent Silicon Corporation | And 2 more authors.
ECS Journal of Solid State Science and Technology | Year: 2013

The effect of ultrahigh temperature rapid thermal oxidation (RTO) on the behavior of oxygen precipitates in Czochralski silicon (Cz-Si) wafers was investigated using infrared (IR) tomography. Dense oxygen precipitate nuclei were formed in the bulk of the Cz-Si wafers when the treatment temperature was increased to 1350°C. Furthermore, when ultrahigh-temperature RTO was combined with cooling rates of over 50°C/s, the density of the oxygen precipitate along the radial direction exhibited significant uniformity. It is assumed that the tendency to form oxygen precipitates in Cz-Si wafers during RTO critically depends upon increasing the concentrations of vacancies that form under ultrahigh-temperature conditions and an oxygen atmosphere. Our results clearly indicate that highly dense oxygen precipitate nuclei can uniformly form along the radial direction of the Si wafer during rapid cooling after RTO at temperatures above 1350°C. © 2012 The Electrochemical Society. All rights reserved.


Araki K.,Tokyo University of Science | Araki K.,Covalent Silicon Corporation | Isogai H.,Covalent Silicon Corporation | Takeda R.,Covalent Silicon Corporation | And 2 more authors.
Journal of Crystal Growth | Year: 2011

A high-temperature annealing method was developed to obtain an atomically flat surface for Si(1 0 0). Maintaining a smooth reconstructed surface is very important for restricting accidental oxidation during the unloading process (i.e., reflow oxidation) after high-temperature annealing. We evaluated the thickness of the reflow oxidation layer and the surface structure obtained on a Si(1 0 0) wafer when we replaced the injected Ar gas with H2 during the cooling process after high-temperature Ar annealing. A H-terminated Si(1 0 0) surface was formed by H2 annealing during the cooling process, and this formation effectively suppressed reflow oxidation. However, the H 2 atmosphere also caused etching of the reconstructed Si(1 0 0) surface; nevertheless, atomic force microscopy (AFM) measurements revealed that the Si(1 0 0) surface roughness drastically decreased when subsequent roughness variation regarded as being caused by the oxidation occurred. The results suggest that our method is effective in restraining increases in surface roughness at the atomic level that are caused by oxidation. © 2010 Elsevier B.V. All rights reserved.


Nakatsuka O.,Nagoya University | Takeuchi S.,Nagoya University | Takeuchi S.,Covalent Silicon Corporation | Shimura Y.,Nagoya University | And 3 more authors.
Key Engineering Materials | Year: 2011

We have investigated the growth and crystalline structures of Ge 1-xSnx buffer and tensile-strained Ge layers for future use in CMOS technology. We have demonstrated that strain relaxed Ge 1-xSnx layers with an Sn content of 12.3% and 9.2% can be grown on Ge and Si substrates, respectively. We achieved a tensile-strain value of 0.71 % in Ge layers on a Ge0.932Sn0.068 buffer layer. We have also investigated the effects of Sn incorporation into Ge on the electrical properties of Ge1-xSnx heteroepitaxial layers.


Araki K.,Tokyo University of Science | Araki K.,Covalent Silicon Corporation | Isogai H.,Covalent Silicon Corporation | Takeda R.,Covalent Silicon Corporation | And 3 more authors.
Japanese Journal of Applied Physics | Year: 2010

It is well known that a smooth surface can be realized for silicon (Si) wafers by Si surface reconstruction using high-temperature annealing. We previously reported that it is crucial to maintain a smooth reconstructed surface to restrict accidental oxidation during the unloading process (i.e., reflow oxidation) in high-temperature annealing. The surface roughnesses of both Si(100) and Si(110) were proved by suppressing the reflow oxidation. Furthermore, for suppressing the reflow oxidation, we evaluated the thickness of the reflow oxidation layer and the surface structure of the Si(110) wafer by replacing the injected Ar gas with H2 in the cooling process during high-temperature Ar annealing. The H2 atmosphere condition induced a change by etching the reconstructed surface, and the H-terminated surface on Si(110) formed SiH2, which effectively suppressed the reflow and characteristic line oxidations, resulting in a smooth terrace-and-step structure. © 2010 The Japan Society of Applied Physics.


Shimura Y.,Nagoya University | Shimura Y.,Japan Society for the Promotion of Science | Takeuchi S.,Covalent Silicon Corporation | Nakatsuka O.,Nagoya University | And 2 more authors.
Solid-State Electronics | Year: 2011

We have investigated how to realize a strain-relaxed Ge1- xSnx layer with large in-plane lattice constant as a buffer layer for a tensile-strained Ge layer. This paper reports the dependence of strain relaxation behavior in Ge1-xSnx layers on the misfit strain at the interface between Ge1- xSnx layers and substrates. We examined control of the misfit strain by growth of Ge1-xSnx layers on bulk-Si and virtual Ge substrates. Large misfit strain between the Ge 1-xSnx layer and the Si substrate leads to strain relaxation during growth and high degree of strain relaxation after annealing. However, it also leads to interfacial mixing and surface roughening with annealing. As a result, the Ge1-xSnx layer having a Sn content of 9.2% was achieved, and it has a potential to induce a tensile strain of 0.99% in Ge layer. © 2011 Elsevier Ltd. All rights reserved.


Patent
Covalent Silicon Corporation | Date: 2012-09-25

A method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD density along a diameter of a bulk of the wafer grown by the CZ process can be improved. Further, a method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD size can also be improved and COP of a surface layer of the wafer can be reduced. The method includes a step of a first heat treatment in which the CZ silicon wafer is heated to a temperature from 1325 to 1400 C. in an oxidizing gas atmosphere, held at the temperature, and then cooled at a cooling rate of from 50 to 250 C./second, and a step of a second heat treatment in which the wafer is heated to a temperature from 900 to 1200 C. in a non-oxidizing gas atmosphere, held at the temperature, and then cooled.

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