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Niigata-shi, Japan

Nakatsuka O.,Nagoya University | Takeuchi S.,Nagoya University | Takeuchi S.,Covalent Silicon Corporation | Shimura Y.,Nagoya University | And 3 more authors.
Key Engineering Materials | Year: 2011

We have investigated the growth and crystalline structures of Ge 1-xSnx buffer and tensile-strained Ge layers for future use in CMOS technology. We have demonstrated that strain relaxed Ge 1-xSnx layers with an Sn content of 12.3% and 9.2% can be grown on Ge and Si substrates, respectively. We achieved a tensile-strain value of 0.71 % in Ge layers on a Ge0.932Sn0.068 buffer layer. We have also investigated the effects of Sn incorporation into Ge on the electrical properties of Ge1-xSnx heteroepitaxial layers. Source


Shimura Y.,Nagoya University | Shimura Y.,Japan Society for the Promotion of Science | Takeuchi S.,Covalent Silicon Corporation | Nakatsuka O.,Nagoya University | And 2 more authors.
Solid-State Electronics | Year: 2011

We have investigated how to realize a strain-relaxed Ge1- xSnx layer with large in-plane lattice constant as a buffer layer for a tensile-strained Ge layer. This paper reports the dependence of strain relaxation behavior in Ge1-xSnx layers on the misfit strain at the interface between Ge1- xSnx layers and substrates. We examined control of the misfit strain by growth of Ge1-xSnx layers on bulk-Si and virtual Ge substrates. Large misfit strain between the Ge 1-xSnx layer and the Si substrate leads to strain relaxation during growth and high degree of strain relaxation after annealing. However, it also leads to interfacial mixing and surface roughening with annealing. As a result, the Ge1-xSnx layer having a Sn content of 9.2% was achieved, and it has a potential to induce a tensile strain of 0.99% in Ge layer. © 2011 Elsevier Ltd. All rights reserved. Source


Patent
Covalent Silicon Corporation | Date: 2012-09-25

A method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD density along a diameter of a bulk of the wafer grown by the CZ process can be improved. Further, a method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD size can also be improved and COP of a surface layer of the wafer can be reduced. The method includes a step of a first heat treatment in which the CZ silicon wafer is heated to a temperature from 1325 to 1400 C. in an oxidizing gas atmosphere, held at the temperature, and then cooled at a cooling rate of from 50 to 250 C./second, and a step of a second heat treatment in which the wafer is heated to a temperature from 900 to 1200 C. in a non-oxidizing gas atmosphere, held at the temperature, and then cooled.


Sakai A.,Osaka University | Yamasaka S.,Osaka University | Kikkawa J.,Osaka University | Takeuchi S.,Osaka University | And 5 more authors.
ECS Transactions | Year: 2012

Wafer bonding is an attractive process to creat new structures and materials, alternative to conventional bulk-Si substrates, in the form of substrates for the advanced metal-oxide-semiconductor field effect transistors (MOSFETs). A germanium on insulator (GOI) substrate attracts much attention because it makes the best use of the higher carrier mobility advantages compared with Si, and is suitable to further downscaling of Ge MOSFET dimensions. However, careful consideration is given especially to the bonded interface between Ge and buried oxide, which should have a device grade quality. In this work, we fabricate GOI substrates by using a wafer bonding method. Atomic structures, chemistry, and electrical properties of the Ge/BOX interface are also characterized. © The Electrochemical Society. Source


Takeuchi S.,Nagoya University | Takeuchi S.,Covalent Silicon Corporation | Shimura Y.,Nagoya University | Shimura Y.,Japan Society for the Promotion of Science | And 14 more authors.
Solid-State Electronics | Year: 2011

In this paper, we propose the fabrication of whole strained Ge complementary metal-oxide-semiconductor (CMOS) with Ge1- xSnx materials as stressors to outperform the state-of-the-art uniaxial compressive strained Si CMOS. Ge1- xSnx materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Firstly, we have demonstrated p-type doped Ge1-xSnx growth by using either B implantation or in situ Ga doping technique. In the B-implanted Ge1-xSnx formation case, fully strained B-doped Ge1-xSnx layers with no Sn precipitation can be obtained even after solid phase epitaxial regrowth (SPER). However, the serious dislocation generation in the layer was occurred during SPER. This is caused by the point defects introduced by B implantation. In order to avoid this crystal damage, we have also demonstrated in situ Ga-doped Ge1- xSnx growth. In this case, we can achieve fully strained Ga-doped Ge1-xSnx growth without Sn precipitation and any defect generation. Secondary, we have demonstrated the formation of Ni(Ge1-ySny) layers for metal/semiconductor contact and investigated the crystalline qualities. The formation of polycrystalline Ni(Ge1-ySny) layers on Ge1-xSnx layers with Sn contents ranging from 2.0% to 6.5% after annealing at from 350 °C to 550 °C can be achieved. Additionally, in the case of the Ni/Ge1- xSnx/Ge sample with a Sn content of 3.5%, an epitaxial Ni2(Ge1-ySny) layer on a Ge 1-xSnx layer was formed. However, the surface roughness due to the agglomeration of Ni(Ge1-xSn x) increases with increasing the Sn content and the annealing temperature. Therefore, a low thermal budget must be required for the formation of Ni(Ge1-xSnx) with high Sn content. © 2011 Elsevier Ltd. All rights reserved. Source

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