Niigata-shi, Japan
Niigata-shi, Japan

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Vincent B.,IMEC | Shimura Y.,Nagoya University | Shimura Y.,Japan Society for the Promotion of Science | Takeuchi S.,Nagoya University | And 14 more authors.
Microelectronic Engineering | Year: 2011

In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate that a minimum of 5% Sn is required in the GeSn source/drain to build a competitive strained Ge pMOSFETs with respect to strained Si channels. Therefore the compatibility of GeSn (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied. A low thermal budget has been determined for those processes on GeSn alloys: temperatures must be lower than 600 °C for B activation and lower than 450 °C for NiGeSn formation. © 2010 Elsevier B.V. All rights reserved.


Yamaha T.,Nagoya University | Nakatsuka O.,Nagoya University | Takeuchi S.,Covalent Silicon Corporation Co. | Takeuchi W.,Nagoya University | And 4 more authors.
ECS Transactions | Year: 2012

We have examined the epitaxial growth of Ge1-x-ySi xSny layers on Ge substrates with a Sn content of 3~15% with low temperature molecular beam epitaxy method. The Ge 1-x-ySixSnylayers are psuedomorphically grown on Ge substrates with high crystalline quality. The surface morphology of the v layers with a Sn content below 7% shows very flat and uniform, although surface roughening occurs in the sample with a Sn content as high as 15% provably due to the Sn precipitation. We also roughly estimated the energy band structure with liner approximation calculation. The energy bandgap of Ge1-x-ySi xSny alloy prepared in this study is expected to be 0.8~1.0 eV at the L or X point. © The Electrochemical Society.


Zaima S.,Nagoya University | Nakatsuka O.,Nagoya University | Shimura Y.,Nagoya University | Shimura Y.,Japan Society for the Promotion of Science | And 11 more authors.
ECS Transactions | Year: 2011

In this paper, we reports our recent studies of the electrical and crystalline properties of heteroepitaxial Ge 1-xSn x layers with various Sn content of 0-25%. We examined Ga-doping in strained Ge 1-xSn x layers for developing source/drain stressor in CMOS applications and investigated the effect of Sn on the doping profile. The impact of Sn on carrier properties has been also studied with the Hall measurement of Ge 1-xSn x/SOI structures. Also, we achieved the epitaxial growth of Ge 1-xSn x layers with a Sn content as high as 25% on InP considering misfit between the epitaxial layer and substrate. ©The Electrochemical Society.


Iwasaki Y.,Osaka University | Nakamura Y.,Osaka University | Kikkawa J.,Osaka University | Sato M.,Covalent Silicon Co. | And 4 more authors.
Japanese Journal of Applied Physics | Year: 2011

The electrical characteristics of wafer-bonded non-doped germanium-on-insulator (GOI) substrates were investigated using a four-point-probe pseudo-metal-oxide-semiconductor field-effect transistor. Annealing the wafer-bonded GOI substrates in vacuum strongly influenced their electrical characteristics. GOI samples annealed at temperatures below 500 °C exhibited n-channel depletion transistor operation, whereas GOI samples annealed at temperatures between 550 and 600 °C exhibited p-channel depletion transistor operation. The carrier mobility strongly depended on the sweep direction of the gate voltage; this characteristic disappeared after annealing at temperatures above 550 °C. The dependence of the electrical characteristics on the annealing temperature is explained in terms of the influence of the defect states on energy band bending near the interface. © 2011 The Japan Society of Applied Physics.


Yoshitake O.,Osaka University | Kikkawa J.,Osaka University | Nakamura Y.,Osaka University | Toyoda E.,Covalent Silicon Co. | And 3 more authors.
Japanese Journal of Applied Physics | Year: 2011

We have investigated annealing effects on Ge/SiO2 interfaces in wafer-bonded germanium-on-insulator substrates using transmission electron microscopy and electron energy loss spectroscopy. A number of nanometer-sized hollows were observed at the Ge/SiO2 interfaces after annealing at 500 and 600 °C, while the density of these hollows was very small after annealing at 700 and 800 °C. The hollows are attributed to the formation of amorphous oxides of Si-rich Si1-xGexO2. The mechanism for the formation and disappearance of these amorphous hollows on the Ge substrates is discussed. © 2011 The Japan Society of Applied Physics.


Takeuchi S.,Nagoya University | Takeuchi S.,Covalent Silicon Co. | Shimura Y.,Nagoya University | Nishimura T.,Nagoya University | And 12 more authors.
ECS Transactions | Year: 2010

In this paper, we propose the fabrication of strained Ge complementary metal-oxide-semiconductor (CMOS) with Ge1-xSnx materials as embedded stressors to outperform the state-of-the-art strained Si CMOS. Ge1-xSnx materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Compatibility of Ge1-xSnx (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation, in situ Ga doping, and Ni(Ge1-ySny) formation) is characterized. A low thermal budget has been determined for those processes on Ge1-xSnx alloys: temperatures must be lower than 600°C for B activation and lower than 450°C for Ni(Ge1-ySny) formation. ©The Electrochemical Society.


Shimura Y.,Nagoya University | Takeuchi S.,Nagoya University | Takeuchi S.,Covalent Silicon Co | Nakatsuka O.,Nagoya University | Zaima S.,Nagoya University
ECS Transactions | Year: 2010

We have investigated the dependence of strain relaxation behavior of Ge1-xSnx layers on the misfit strain at the interface between Ge1-x Snx layers and substrates. When the large misfit strain was induced, surface roughening and degradation of the crystallinity occurred during the Ge1-xSnx growth. We found that the universal dependency of the strain relaxation behavior, which is independent on kinds of substrates. As a result, the Ge1-xSn x layer having a Sn content of 12.3% was achieved, which has a potential to induce a tensile strain of 1.28% in a Ge layer. ©The Electrochemical Society.


Yamashita M.,Osaka University | Nakamura Y.,Osaka University | Nakamura Y.,Japan Science and Technology Agency | Sugimoto R.,Osaka University | And 3 more authors.
Applied Surface Science | Year: 2013

We investigated the formation mechanism of peculiar structures on vicinal Si(1 1 0) surfaces caused by annealing. The shapes of the peculiar structures strongly depended on the tilt angle of the vicinal surface from the exact Si(1 1 0) surface. The size of these structures varied with temperature and pressure during annealing. The dependence of the peculiar structure size on the annealing conditions can be explained by considering nucleation of the peculiar structures that is strongly related to Si surface diffusion during the annealing. © 2012 Elsevier B.V. All rights reserved.


Merckling C.,IMEC | Sun X.,Catholic University of Leuven | Sun X.,Yale University | Shimura Y.,Nagoya University | And 9 more authors.
Applied Physics Letters | Year: 2011

We investigated the molecular beam deposition of Al2 O 3 on Ge0.95 Sn0.05 surface with and without an ultra thin Ge cap layer in between. We first studied the atomic configuration of both Ge1-x Snx and Ge/ Ge1-x Snx surfaces after deoxidation by reflection high-energy electron diffraction and resulted, respectively, in a c (4×2) and (2×1) surface reconstructions. After in situ deposition of an Al2 O3 high- κ gate dielectric we evidenced using time-of-flight secondary ion mass spectroscopy analyses that Sn diffusion was at the origin of high leakage current densities in the Ge1-x Snx / Al2 O3 gate stack. This damage could be avoided by inserting a thin 5-nm-thick Ge cap between the oxide and the Ge1-x Snx layer. Finally, metal-oxide-semiconductor capacitors on the Ge capped sample showed well-behaved capacitance-voltage (C-V) characteristics with interface trap density (D it) in the range of 1012 eV-1 cm-2 in mid gap and higher close to the valence band edge. © 2011 American Institute of Physics.


Minami K.,Osaka University | Nakamura Y.,Osaka University | Nakamura Y.,Japan Science and Technology Agency | Yamasaka S.,Osaka University | And 4 more authors.
Thin Solid Films | Year: 2012

The electrical properties of wafer-bonded n-type Ge(111)-on-insulator (Ge(111)-OI) substrates were characterized using a four-point-probe pseudo-metal-oxide-semiconductor field-effect transistor (pseudo-MOSFET) method. Average electron and hole mobilities in the Ge(111)-OI channel were measured to be ∼1000 cm 2/V s in accumulation mode and ∼310 cm 2/V s in inversion mode, respectively. The measured mobility strongly depended on the sample position, due to the spatially inhomogeneous distribution of the interface states. Despite the existence of interface states, the carrier mobility exhibited a high value demonstrating the prospect of wafer-bonded Ge(111)-OI as a channel material in MOSFETs. © 2011 Elsevier B.V. All rights reserved.

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