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Devarapalli S.V.,Xilinx Inc. | Zarkesh-Ha P.,University of New Mexico | Suddarth S.C.,COSMIAC
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | Year: 2010

Aggressive device scaling has reduced the gate capacitance, which resulted in increasing sensitivity to radiation induced soft errors. In addition, technology scaling has reached to the point of maximum clock frequency to maintain acceptable energy consumption. On the other hand, technology advancements are demanding higher throughput and data rates. To mitigate these problems, we propose a unique single event upset (SEU) hardened dual data rate (DDR) flip-flop using c-elements, "Firebird". Unlike the existing rad-hard flip-flops, the proposed Firebird design not only is truly protected to SEUs, but it also latches in both rising and falling edges of the clock for DDR operation. With the use of DDR, the clock frequency (activity) can be reduced by 2x with no impact on performance. In comparison with the simplified Built-in Soft Error Resilient Flip-Flop (B-SER-FF) with DDR at 45nm CMOS process, the proposed Firebird design consumes 19.6% less power, with 9.5% high C2Q delay. The power-delay product of the proposed Firebird design is 11.2% better than its counterpart, B-SER-FF with DDR. © 2010 IEEE.

Mayberry C.,U.S. Air force | Nguyen D.D.,COSMIAC | Kouhestani C.,COSMIAC | Kambour K.E.,SAIC | And 2 more authors.
ECS Transactions | Year: 2012

The increase in the magnitude of the threshold voltage of a positive-channel metal oxide semiconductor (PMOS) under negative gate biasing (negative bias temperature instability) is attributed to the build-up of charge in the gate insulator. We have studied the charging and discharging of nitrided SiO2 gate insulator field effect transistors and through the use of pseudo-DC and pulsed stressing methods, have extracted, at least, three charging components. These components are (a) the charging of interface states at the semiconductor/insulator boundary, (b) dynamically recoverable positive charging in the bulk' of the insulator, and (c) positive charging in the insulator, which can be eliminated' only by application of a positive electric field across the insulator. It is proposed that the charge elimination' in (c) arises via a charge neutralization process involving electron capture at switching traps, as opposed to de-trapping, and that this can be reversed by the application of a small negative field. © The Electrochemical Society.

Kambour K.,SAIC | Rosen N.,Air Force Research Lab | Kouhestani C.,COSMIAC | Nguyen D.,COSMIAC | And 6 more authors.
IEEE Transactions on Nuclear Science | Year: 2012

Initial experimental work has demonstrated that X-ray bombardment of organic-based photocells (specifically P3HT:PCBM-based) leads to a reduction in the open-circuit voltage (Voc) without apparent change in the carrier relaxation time. The variation of Voc was suggested to be due to the injection and trapping of holes near the anode, which resulted in a decrease in the built-in potential. We have extended the experimental measurements to higher total dose (∼ 1300(SiO2)). Using standard inorganic modeling tools, a device model of the organic cell has been developed and predictions made. These predictions have been compared to the results of the previous and new experimental measurements and they demonstrate reasonable agreement between the two, thereby supporting the initial charge buildup hypothesis. Questions about the origin and behavior of the photo-carrier relaxation arise. © 1963-2012 IEEE.

Nguyen D.D.,COSMIAC | Kouhestani C.,COSMIAC | Kambour K.E.,Leidos | Devine R.A.B.,Think Strategically
Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics | Year: 2014

Using a rapid data acquisition methodology, the authors examine the time dependent recovery of the "permanent" component of charge build-up due to the negative bias temperature instability in Si based p-channel field effect transistors in inversion and n-channel devices in accumulation. The authors find clear evidence for recovery of the charge associated with interface states for elevated temperatures (≥150 °C) and for extended times (trecover ∼ 20 000 s). Recovery appears to begin at shorter times for p-channel devices than for n-channel. An explanation is advanced both for the mechanism of interface state annealing and for the difference observed between p and n channel devices. © 2014 American Vacuum Society.

Kambour K.E.,Leidos | Kouhestani C.,TEAM Technologies Inc. | Nguyen D.D.,COSMIAC | Devine R.A.B.,Think Strategically
Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics | Year: 2016

The need for more reliable and radiation hard complementary metal-oxide-semiconductor compatible devices coupled with an ever increasing shrinkage of device dimensions has led naturally to interest in metal-oxide semiconductor field-effect transistors having nontraditional geometries. One such geometry is the gate-all-around transistor, which has been suggested to be less sensitive than its planar counterpart to the effect of charge build-up at the semiconductor-insulator interface such as that induced by irradiation. In order to explore the radiation hardness of such a structure, the effect of radiation on gate-all-around n-type metal-oxide-semiconductor devices was investigated by computing the effect of charging on the threshold voltage of the device. The radiation sensitivity in ideal structures is explored, and the greater radiation sensitivity found experimentally in some devices is explained. © 2016 American Vacuum Society.

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