Kirtland, NM, United States
Kirtland, NM, United States
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Nguyen D.D.,COSMIAC | Kouhestani C.,COSMIAC | Kambour K.E.,Leidos | Devine R.A.B.,Think Strategically
Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics | Year: 2014

Using a rapid data acquisition methodology, the authors examine the time dependent recovery of the "permanent" component of charge build-up due to the negative bias temperature instability in Si based p-channel field effect transistors in inversion and n-channel devices in accumulation. The authors find clear evidence for recovery of the charge associated with interface states for elevated temperatures (≥150 °C) and for extended times (trecover ∼ 20 000 s). Recovery appears to begin at shorter times for p-channel devices than for n-channel. An explanation is advanced both for the mechanism of interface state annealing and for the difference observed between p and n channel devices. © 2014 American Vacuum Society.

Kambour K.E.,Leidos | Kouhestani C.,TEAM Technologies Inc. | Nguyen D.D.,COSMIAC | Devine R.A.B.,Think Strategically
Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics | Year: 2016

The need for more reliable and radiation hard complementary metal-oxide-semiconductor compatible devices coupled with an ever increasing shrinkage of device dimensions has led naturally to interest in metal-oxide semiconductor field-effect transistors having nontraditional geometries. One such geometry is the gate-all-around transistor, which has been suggested to be less sensitive than its planar counterpart to the effect of charge build-up at the semiconductor-insulator interface such as that induced by irradiation. In order to explore the radiation hardness of such a structure, the effect of radiation on gate-all-around n-type metal-oxide-semiconductor devices was investigated by computing the effect of charging on the threshold voltage of the device. The radiation sensitivity in ideal structures is explored, and the greater radiation sensitivity found experimentally in some devices is explained. © 2016 American Vacuum Society.

Kambour K.E.,Leidos | Nguyen D.D.,COSMIAC | Kouhestani C.,COSMIAC | Devine R.A.B.,Think Strategically
IEEE International Integrated Reliability Workshop Final Report | Year: 2013

The generation of interface states created by depassivating dangling bonds at the interface between the gate dielectric and silicon substrate is important for both the growth of Negative Bias Temperature Instability threshold voltage shift in MOSFETs and the radiation sensitivity of the devices. In this paper we present results comparing the generation of interface states for both processes and their possible annealing at high temperatures. © 2013 IEEE.

Nguyen D.D.,COSMIAC | Kouhestani C.,COSMIAC | Kambour K.E.,Leidos | Devine R.A.B.,Think Strategically
IEEE International Integrated Reliability Workshop Final Report | Year: 2013

This paper reports new high temperature measurements of Negative Bias Temperature Instability induced interface states in both NMOS and PMOS devices. Evidence of annealing of the interface states, previously thought to be 'permanent', is presented for measurements including a methodology which allows the direct measurement of the time dependent growth/recovery of the interface state component. © 2013 IEEE.

Nguyen D.D.,COSMIAC | Kambour K.E.,Leidos | Kouhestani C.,COSMIAC | Devine R.A.B.,Think Strategically
ECS Transactions | Year: 2014

We have performed negative and positive bias temperature instability (NBTI and PBTI) measurements on devices having different gate oxide types and thicknesses. The devices used for the study include 130nm and 90 nm oxynitrided gate dielectric bulk Si technology and devices with pure SiO2 gate dielectric. NBTI and PBTI were studied for both p-channel and n-channel MOSFETs for each of the oxide types and thicknesses, this requires the measurements be made in both accumulation and inversion modes. Using "Pseudo DC" measurements at 120 ° C on p-channel and n-channel devices, we have extracted at least three distinct components of BTI. We find evidence for the existence of positive charge injection for PMOS under PBTI and more puzzling results for NMOS under PBTI, where unexpected interface state creation was observed. © 2014 by The Electrochemical Society. All rights reserved.

News Article | February 24, 2017

The University of New Mexico has been awarded a $7 million grant from the Air Force Research Laboratory to develop and build new materials and devices for electronics in space. The five-year contract was awarded this month to COSMIAC, a research center in UNM’s School of Engineering. The grant is part of an AFRL project that will build faster electrical devices that are better-suited for space satellites. Researchers on the project will focus on developing alternative semiconductor materials for electronics that perform better than current materials in the harsh conditions of a space environment. “This is one of the largest awards the School of Engineering has ever received, and this is an incredible opportunity to not just make an impact in the area of space materials but to showcase our capabilities in the School of Engineering,” says Christos Christodoulou, principal investigator on the project. “This is an important project that will strive to produce more robust space electronics, which will vastly improve the capabilities of satellites.” Christodoulou, also a Distinguished Professor in the Department of Electrical and Computer Engineering and associate dean for research in the School of Engineering, will work with co-principal investigators Ganesh Balakrishnan and Payman Zarkesh-Ha, both professors of electrical and computer engineering, on the project. UNM was chosen after a national competition for the contract. A major factor that contributed to AFRL giving the University the project was the capabilities offered at the Center for High Technology Materials, a university-wide research center. UNM is one of the few universities in the United States with the nanoscale design and fabrication capabilities needed for the project. In 2010, UNM acquired a $1.5 million molecular beam epitaxy machine that can build up semiconductor nanocrystals one atom at a time to develop new materials. For the project, the UNM team will study advanced semiconductor elements, such as antimonide or gallium arsenide and nitride, as possible alternatives to silicon to create new foundations for electronic devices. Those materials could conduct electricity faster than silicon and offer better protection against radiation and other adverse conditions in space. Outside of the research mission, Christodoulou said a possible future outcome of this project would be to develop a specialized online master’s program in space electronics, as well as to boost economic development in New Mexico.

Devarapalli S.V.,Xilinx Inc. | Zarkesh-Ha P.,University of New Mexico | Suddarth S.C.,COSMIAC
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | Year: 2010

Aggressive device scaling has reduced the gate capacitance, which resulted in increasing sensitivity to radiation induced soft errors. In addition, technology scaling has reached to the point of maximum clock frequency to maintain acceptable energy consumption. On the other hand, technology advancements are demanding higher throughput and data rates. To mitigate these problems, we propose a unique single event upset (SEU) hardened dual data rate (DDR) flip-flop using c-elements, "Firebird". Unlike the existing rad-hard flip-flops, the proposed Firebird design not only is truly protected to SEUs, but it also latches in both rising and falling edges of the clock for DDR operation. With the use of DDR, the clock frequency (activity) can be reduced by 2x with no impact on performance. In comparison with the simplified Built-in Soft Error Resilient Flip-Flop (B-SER-FF) with DDR at 45nm CMOS process, the proposed Firebird design consumes 19.6% less power, with 9.5% high C2Q delay. The power-delay product of the proposed Firebird design is 11.2% better than its counterpart, B-SER-FF with DDR. © 2010 IEEE.

Costantine J.,American University of Beirut | Tawk Y.,COSMIAC | Tawk Y.,Notre Dame University - Louaize | Maqueda I.,California Institute of Technology | And 4 more authors.
IEEE Transactions on Antennas and Propagation | Year: 2016

The design process and the deployment mechanism of a quadrifilar helix antenna (QHA) and a conical log spiral antenna (CLSA) are presented. The two antennas are proposed to operate in the UHF frequency band. They are composed of conductors that are embedded and supported by innovative structural techniques. This allows efficient folding, packaging, and deployment once in space. The conductors in the QHA are composed of beryllium copper and are supported by helical arms of S2 glass fiber reinforced epoxy. The CLSA, on the other hand, has conductors that are made out of a mesh of phosphor bronze and incorporated inside thin insulators composed of continuous fiber composites. The new aspects of these designs lie in their structures and deployment mechanisms. The deployment mechanisms for both antennas include helical pantograph and origami patterns such as Z-folding configurations. Both antennas are fabricated and tested for both deployment and radiation performance. A comparison is executed between both designs, and their potential deployment possibilities from CubeSats are also investigated. © 2016 IEEE.

Kief C.J.,COSMIAC | Zufelt B.K.,COSMIAC | Christensen J.H.,Utah State University | Mee J.K.,Air Force Research Lab
AIAA Infotech at Aerospace Conference and Exhibit 2011 | Year: 2011

The Space Plug-and-play Architecture (SPA) concept of rapid satellite development has progressed exponentially over the past several years. The team at the Configurable Space Microsystems Innovations and Applications Center (COSMIAC) in conjunction with the Space Dynamics Laboratory (SDL) and the Air Force Research Laboratory have trained over 500 individuals on this rapid bus architecture related to satellite development. This paper will outline the first CubeSat satellite proof of concept flight for a SPA only spacecraft. The Trailblazer mission is designed to fly a 1U CubeSat that is based entirely on a SPA bus implementation. Trailblazer will consist of Commercial Off The Shelf (COTS) parts converted to be SPA compliant. This allows not only a demonstration of the bus reliability in a space environment, but also the ease in converting existing components to be SPA compliant. With the dimensional constraints and power budget of Trailblazer, we have elected to use the SPA-1 standard. SPA-1 is the most recent addition to the AFRL SPA family. The SPA-1 data transfer protocol is based on 400 kbit/s I2C making it the lowest power, and lowest bandwidth option for SPA. Given the power constraints of typical satellite architecture, it is generally advantageous to interface devices/modules which do not require high data transfer rates to a SPA network via the SPA-1 Applique Sensor Interface Module (ASIM). This ASIM is logic that enables SPA Plug-and-Play for hardware components. It contains all the information needed for the system to automatically discover and automatically configure the hardware component. SPA-1 ASIMs can be any microcontroller that supports I2C and has enough memory to contain the needed logic. This allows the standard to remain open to a variety of dynamic implementations. The Trailblazer mission is being launched under the National Aeronautics and Space Administration (NASA) Educational Launch of Nanosatellite (ELaNA) program. This NASA program is designed to provide affordable access to space through collaborative efforts with academic institutions. The ELaNA program provides manifesting and launch of CubeSats for $30,000 per 1U module. The proposed orbit is 325 km with an inclination of 51 degrees for a launch in 2011. © 2011 by Craig Kief.

Mayberry C.,U.S. Air force | Nguyen D.D.,COSMIAC | Kouhestani C.,COSMIAC | Kambour K.E.,SAIC | And 2 more authors.
ECS Transactions | Year: 2012

The increase in the magnitude of the threshold voltage of a positive-channel metal oxide semiconductor (PMOS) under negative gate biasing (negative bias temperature instability) is attributed to the build-up of charge in the gate insulator. We have studied the charging and discharging of nitrided SiO2 gate insulator field effect transistors and through the use of pseudo-DC and pulsed stressing methods, have extracted, at least, three charging components. These components are (a) the charging of interface states at the semiconductor/insulator boundary, (b) dynamically recoverable positive charging in the bulk' of the insulator, and (c) positive charging in the insulator, which can be eliminated' only by application of a positive electric field across the insulator. It is proposed that the charge elimination' in (c) arises via a charge neutralization process involving electron capture at switching traps, as opposed to de-trapping, and that this can be reversed by the application of a small negative field. © The Electrochemical Society.

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