Drzevitzky S.,Computer Engineering Group |
Kastens U.,Computer Engineering Group |
Platzner M.,Computer Engineering Group
International Journal of Reconfigurable Computing | Year: 2010
Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at runtime provides these systems with an unparalleled degree of adaptivity but at the same time poses new challenges for security and safety. In this paper, we elaborate on the presentation of proof carrying hardware (PCH) as a novel approach to reconfigurable system security. PCH takes a key concept from software security, known as proof-carrying code, into the reconfigurable hardware domain. We outline the PCH concept and discuss runtime combinational equivalence checking as a first online verification problem applying the concept. We present a prototype tool flow and experimental results demonstrating the feasibility and potential of the PCH approach. © 2010 Stephanie Drzevitzky et al.
Pasin M.,Federal University of Santa Maria |
Scheuermann B.,Computer Engineering Group |
Moura R.F.D.,Federal University of Santa Maria
Proceedings - 2015 8th IFIP Wireless and Mobile Networking Conference, WMNC 2015 | Year: 2015
Efficient intersection control represents a major challenge in traffic management, as it can contribute to reducing traffic congestion and travel times. Communicating vehicles, for instance using VANETs, open up new opportunities for intersection control, providing fairness and throughput to transportation networks. In this paper, we are interested in the tradeoffs between fairness and throughput in intersection control. Our key contributions are (i) novel intersection control algorithms which consider both fairness and throughput, and (ii) a simulative evaluation which compares these algorithms with other solutions. We evaluate the algorithms in a comparative simulation study, using microscopic traffic simulation and considering different traffic demands. © 2015 IEEE.
Happe M.,Computer Engineering Group |
Lubbers E.,Airbus |
Platzner M.,Computer Engineering Group
Journal of Real-Time Image Processing | Year: 2013
Sequential Monte Carlo (SMC) represents a principal statistical method for tracking objects in video sequences by on-line estimation of the state of a non-linear dynamic system. The performance of individual stages of the SMC algorithm is usually data-dependent, making the prediction of the performance of a real-time capable system difficult and often leading to grossly overestimated and inefficient system designs. Also, the considerable computational complexity is a major obstacle when implementing SMC methods on purely CPU-based resource constrained embedded systems. In contrast, heterogeneous multi-cores present a more suitable implementation platform. We use hybrid CPU/FPGA systems, as they can efficiently execute both the control-centric sequential as well as the data-parallel parts of an SMC application. However, even with hybrid CPU/FPGA platforms, determining the optimal HW/SW partitioning is challenging in general, and even impossible with a design time approach. Thus, we need self-adaptive architectures and system software layers that are able to react autonomously to varying workloads and changing input data while preserving real-time constraints and area efficiency. In this article, we present a video tracking application modeled on top of a framework for implementing SMC methods on CPU/FPGA-based systems such as modern platform FPGAs. Based on a multithreaded programming model, our framework allows for an easy design space exploration with respect to the HW/SW partitioning. Additionally, the application can adaptively switch between several partitionings during run-time to react to changing input data and performance requirements. Our system utilizes two variants of a add/remove self-adaptation technique for task partitioning inside this framework that achieve soft real-time behavior while trying to minimize the number of active cores. To evaluate its performance and area requirements, we demonstrate the application and the framework on a real-life video tracking case study and show that partial reconfiguration can be effectively and transparently used for realizing adaptive real-time HW/SW systems. © 2011 Springer-Verlag.