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Grant
Agency: European Commission | Branch: H2020 | Program: IA | Phase: ICT-28-2015 | Award Amount: 10.29M | Year: 2016

Photonics is essential in todays life science technology. PIX4life will mature a state of the art silicon nitride (SiN) photonics pilot line for life science applications in the visible range and pave the way to make it accessible as an enabler for product development by a broad range of industrial customers. We aim at 1) establishing a validated CMOS compatible SiN technology platform in the visible range for complex densely integrated photonics integrated circuits (PICs), 2) developing a supply chain to integrate mature semiconductor laser sources and CMOS detector arrays with the SiN PICs on the basis of technologies that are scalable to high volume, 3) establishing appropriate design kits and tools, 4) demonstrating the performance of the pilot line for well-chosen life science applications in the domain of vital sensing, multispectral sources for super-resolution microscopy, cytometry and 3D tissue imaging, 5) setting up the logistics for multi-project-wafer (MPW) access to the pilot line. Integrated photonics has demonstrated that optical functions can be realized in a more compact, robust and cost-effective way by integrating functionalities on a single chip. At present industrialization is limited to telecom applications at infrared wavelengths. The field of life sciences is heavily dependent on bulky and expensive optical systems and would benefit enormously from low cost photonic implementations. However this field requires a visible light PIC-technology. Proof of concept demonstrations are abundant, but pilot line and manufacturing capacity is limited, inhibiting industrial take up. PIX4life will drive the future European RTD in visible photonic applications for life sciences by bridging technological research (via participation of 2 academic and 2 research institutes) towards industrial development (via participation of a foundry, two large companies and 9 fabless SMEs, either technology suppliers or life science end users).


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-01-2014 | Award Amount: 27.39M | Year: 2015

This project will research new technologies for CMOS image sensors that are needed in the next generation of several application domains. The image sensor research will focus on enhancing the capabilities of current imaging devices: New design (architectures) and technology (e.g. 3D stacking) for better pixels (lower noise, higher dynamic range, new functionality within the pixel) and more pixels (higher spatial and temporal resolutions) at higher speed, time-of-flight pixels, local (on-chip) image processing, embedded CCD in CMOS TDI pixels. Extended sensitivity and functionality of the pixels: extension into infrared, filters for hyper-and multi-spectral imaging, better colour filters, programmable filters with LCD cells. Application domains that will be covered are: Digital Lifestyle: Broadcast, Digital Cinema & Entertainment, Smart home (Grass Valley, Angenieux, Silios, Delft University of Technology, SoftKinetic) Smart Production (IMEC, C-cam) High-end Security (Adimec, Angenieux, Le2i, TNO) Agriculture and food sorting using hyper- and multi-spectral imaging and programmable filters (Silios, Le2i) Medical healthcare: diagnostics using multi-/hyper-spectral imaging and programmable filters (Adimec, TNO, Silios, Quest and Focal) Gas detection using multi spectral IR imagers (Sofradir) Security: gas sensing (Sofradir) The prototype CMOS image sensors for several application domains will be demonstrated together with the sensor related processing.


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2011.3.5 | Award Amount: 4.08M | Year: 2012

Along the cancer care workflow, existing preoperative and intraoperative procedures such as the identification of small tumourous areas or the precise resection of tumors show significant fail rates, due to the inability of current imaging techniques to perform a reliable in situ diagnosis. Moreover the complete pathological diagnosis, often based on histology slides preparation, is usually only available after a few days. For these reasons a significant number of patients need to undergo secondary biopsy or surgery.\nThe CAReIOCA project aims at providing pathologists and/or surgeons novel non-invasive optical imaging at the cellular scale for fast cancer assessment. By providing images approaching the level of information of histology slides during localization, biopsy and resection procedures in real or near-real time, the technique is expected to significantly improve cancer care. The project will combine latest advances in CMOS technology and optical biopsy techniques to overcome the current technical limitations of an unequalled performance non-invasive tissue imaging technique: Full-Field Optical Coherence Tomography (FFOCT). The key technological achievement of the project will consist of the development of a specific high-performance CMOS smart camera, and will lead to the development, clinical adaptation and pre-clinical validation of a novel optical biopsy probe, exhibiting in-depth imaging capabilities and a record 3D resolution.\nThe technique will provide a fast and reliable method to visualize pathological or suspicious areas, and corresponding microstructures, in real-time. In particular, it will enable pre-operative diagnosis, biopsy guidance, as well as intra-operative, large-scale surgical margin assessment. These applications are expected to significantly reduce reoperation rates of corresponding procedures. In this view, pre-clinical validation on Oral and Breast Cancer will be performed.


Patent
CMOSIS nv | Date: 2014-01-18

An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.


Patent
CMOSIS nv | Date: 2014-06-04

A pixel array for imaging comprises an array of pixels of a first pixel type (50) and a second pixel type (60, 70; 80). Each pixel of the first pixel type (50) comprises a first photo-sensitive element (51) having a first area. Each pixel of the second pixel type (60, 70; 70) comprises a second photo-sensitive element (61, 71; 81) and a third photo-sensitive element (62, 72; 82). The second photo-sensitive element (61, 71; 81) has a second area, which is smaller than the first area. Only the second photo-sensitive element in the pixel of the second pixel type is connected to a readout circuit. The third photo-sensitive element is connected to a charge drain via a permanent connection or a switchable connection. Outputs of the second photo-sensitive elements (61, 71; 81) can be used to perform phase detect autofocussing.


Patent
CMOSIS nv | Date: 2012-01-05

A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.


Patent
CMOSIS nv | Date: 2011-07-20

A pixel structure comprises a photo-sensitive element (PPD) for generating charge in response to incident light. A first transfer gate (TX1) is connected between the photo-sensitive element (PPD) and a first charge conversion element (FD1). A second transfer gate (TX2) is connected between the photo-sensitive element (PPD) and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element (FD1) and outputs a second value related to charge at the second charge conversion element (FD2). A controller (40) controls operation of the pixel structures and causes a pixel structure. The controller (40) causes the pixel structure to: acquire charges on the photo-sensitive element (PPD) during an exposure period; transfer a first portion of the charges acquired during the exposure period from the photo-sensitive element (PPD) to the first charge conversion element (FD1) via the first transfer gate (TX1); and transfer a second portion of the charges acquired during the exposure period from the photo-sensitive element (PPD) to the second charge conversion element (FD2) via the second transfer gate (TX2).


Patent
CMOSIS nv | Date: 2014-05-02

A pixel comprises a pinned photodiode for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the pinned photodiode and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage.


Patent
CMOSIS nv | Date: 2013-03-20

An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a conversion cycle which has two phases, with the ramp signal being reset between the two phases.. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.


Patent
CMOSIS nv | Date: 2013-05-01

A pixel comprising:a photo-sensitive element for generating charges in response to incident radiation;a sense node;a transfer gate, connected between the photo-sensitive element and the sense node, for controlling transfer of charges to the sense node;a reset switch connected to the sense node for resetting the sense node to a predetermined voltage;a first buffer amplifier having an input connected to the sense node;a first sample stage, connected to an output of the first buffer amplifier, which is selectively operable to sample a value of the sense node;a second sample stage connected in cascade with the first sample stage which is selectively operable to sample a value of the sense node; anda second buffer amplifier having an input connected to the second sample stage;wherein the transfer gate is adapted for transferring substantially all charge from the photosensitive element to the sense node when the transfer gate is opened.

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