Irvine, CA, United States
Irvine, CA, United States

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Patent
ClariPhy Communications | Date: 2016-11-14

A receiver architecture and method recovers data received over an optical fiber channel in the presence of cycle slips. In a first cycle slip recovery architecture, a receiver detects and corrects cycle slips based on pilot symbols inserted in the transmitted data. In a second cycle slip recovery architecture, a coarse cycle slip detection is performed based on pilot symbols and a cycle slip position estimation is then performed based on carrier phase noise. The receiver compensates for cycle slips based on the position estimation.


Patent
ClariPhy Communications | Date: 2013-07-29

A receiver for a communications link includes a receiver module and a host receiver. These two components can be tested independently. In one embodiment, the receiver module is characterized with respect to noise and distortion. The noise performance can be determined by comparing input and output signals of the receiver module, to determine the relative noise of the receiver module. The distortion performance can be determined by comparing the distortion of input and output signals of the receiver module, using a reference host receiver that includes an equalizer. The host receiver can be tested by using a reference receiver module.


Patent
ClariPhy Communications | Date: 2014-09-08

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.


Patent
ClariPhy Communications | Date: 2010-12-13

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.


Patent
ClariPhy Communications | Date: 2016-06-21

A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.


A transmitter for a communications link is tested by using a (software) simulation of a reference channel and/or a reference receiver to test the transmitter. In one embodiment for optical fiber communications links, a data test pattern is applied to the transmitter under test and the resulting optical output is captured, for example by a sampling oscilloscope. The captured waveform is subsequently processed by the software simulation, in order to simulate propagation of the optical signal through the reference channel and/or reference receiver. A performance metric for the transmitter is calculated based on the processed waveform.


A system includes a time-interleaved device. An equalizer effectively can apply different equalization to different interleaved channels. For convenience, these equalizers will be referred to as multi-channel equalizers. In one aspect, an apparatus includes an interleaved device having M interleaved channels, and a multi-channel equalizer coupled to the interleaved device. The multi-channel equalizer is capable of applying a different equalization to different interleaved channels, thus compensating for channel-dependent impairments.


A transmitter for a communications link is tested by using a (software) simulation of a reference channel and/or a reference receiver to test the transmitter. In one embodiment for optical fiber communications links, a data test pattern is applied to the transmitter under test and the resulting optical output is captured, for example by a sampling oscilloscope. The captured waveform is subsequently processed by the software simulation, in order to simulate propagation of the optical signal through the reference channel and/or reference receiver. A performance metric for the transmitter is calculated based on the processed waveform.


A transmitter for a communications link is tested by using a (software) simulation of a reference channel and/or a reference receiver to test the transmitter. In one embodiment for optical fiber communications links, a data test pattern is applied to the transmitter under test and the resulting optical output is captured, for example by a sampling oscilloscope. The captured waveform is subsequently processed by the software simulation, in order to simulate propagation of the optical signal through the reference channel and/or reference receiver. A performance metric for the transmitter is calculated based on the processed waveform.


Patent
ClariPhy Communications | Date: 2016-01-19

A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.

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