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Ben-Romdhane M.,CIRTACOM Research Laboratory | Abeda A.,CIRTACOM Research Laboratory | Rebai C.,CIRTACOM Research Laboratory
Journal of Computers | Year: 2010

This paper proposes a new stable design strategy for 1- bit high order digital Δσ modulator for multistandard fractional-N frequency synthesizer. The proposed digital δσ modulator presents simplicity, low power consumption and controls a dualmodulus divider instead of multi-modulus one as in existing δσ fractional-N frequency synthesizer. Simulation results illustrate the δσ modulator good performances in terms of spectrum purity and accuracy. Using this stable 1-bit digital Δσ modulator output to a fractional-N frequency synthesizer Simulink model verifies the multistandard frequency synthesizer specifications. © 2010 academy publisher.


Maalej A.,CIRTACOM Research Laboratory | Maalej A.,Telecom ParisTech | Manel B.-R.,CIRTACOM Research Laboratory | Desgreys P.,Telecom ParisTech | And 3 more authors.
5th Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2010 | Year: 2010

Non Uniform Sampling (NUS) was presented as an emerging solution to reduce aliases for ADC (Analog-to-Digital Converter) in Software Defined Radio receiver. In this paper, practical implementations of NUS, called TQ-RS (Time Quantized Random Sampling) are presented. A test setup for non uniformly controlled data acquisition system is detailed. Experimental results are presented and discussed. © 2010 IEEE.


Mlayeh Y.,CIRTACOM Research Laboratory | Rouissi F.,CIRTACOM Research Laboratory | Tlili F.,CIRTACOM Research Laboratory | Ghazel A.,CIRTACOM Research Laboratory
5th Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2010 | Year: 2010

This paper proposes an advanced OFDM-MIMO reconfigurable architecture that uses an adaptive switching algorithm between diversity and spatial multiplexing. The transmitter blocs' specifications such as the MIMO technique and the modulation scheme are adjusted according to the channel state, which gives a practical cognitive radio strategy. The system cost-efficiency is performed by the application of the Software Defined Radio (SDR) technology. Based on the Demmel condition number criterion, an indicator bit exchange between the transmitter and the receiver allows selecting the adapted MIMO configuration and improving the whole system performances. © 2010 IEEE.


Souissi S.,CIRTACOM Research Laboratory | Ben Dhia A.,CIRTACOM Research Laboratory | Tlili F.,CIRTACOM Research Laboratory | Rebai C.,CIRTACOM Research Laboratory
5th Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2010 | Year: 2010

Automatic meter reading (AMR) technology allows energy suppliers to exploit their own infrastructure to bill their customers in an efficient and economical way using Power Line Communications (PLC). At this moment, new applications and services are required by market such as load and alarm management, remote monitoring and disconnection, etc. Thus, narrowband PLC modems should satisfy these services, provide high throughput and keep a low cost. In this paper, we propose a design methodology of a narrowband OFDM based PLC modem, its implementation on embedded processor and optimization of three building blocks: FFT, Viterbi, and convolutional encoder. © 2010 IEEE.


Maalej A.,CIRTACOM Research Laboratory | Maalej A.,Telecom ParisTech | Ben-Romdhane M.,CIRTACOM Research Laboratory | Rebai C.,CIRTACOM Research Laboratory | And 3 more authors.
Journal of Computers | Year: 2010

In this paper, a Non-Uniform Sampling (NUS) technique for down-conversion stage in a multistandard radio receiver is proposed. For both narrowband and wideband standard processing, NUS promises relaxing system design constraints, decreasing the sampling frequency as well as reducing power consumption. A non-uniform clock generator, called Pseudorandom Direct Sampler (PDS), is described. PDS is used to non-uniformly control the Analog-to-Digital Converter (ADC) performing IF sub-sampling in proposed GSM/UMTS/WiFi multistandard receiver architecture. PDS architecture is based on using modified Direct Digital Synthesizer (DDS) including pseudorandom behavior. A 90- nm CMOS FPGA based prototype of PDS reveals an internal clocking up to 350 MHz and a power consumption lower than 4 mW. © 2010 Academy Publisher.

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