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Hsinchu, Taiwan

Patent
ChipMOS Technologies | Date: 2014-04-09

The present disclosure relates to a package structure of a lead frame. The package includes a die, a dielectric layer, at least one conducting pillar, at least one lead frame and at least one solder ball. The dielectric layer is disposed on a surface of the die. The at least one conducting pillar penetrates through the dielectric layer and is disposed on the surface. The at least one lead frame is disposed on the dielectric layer and is spaced from the at least one conducting pillar with a gap. The solder ball fills the gap and electrically connects the at least one conducting pillar and the at least one lead frame.


Patent
ChipMOS Technologies | Date: 2014-03-05

The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.


Patent
ChipMOS Technologies | Date: 2015-03-12

A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip pad is connected to at least one of the chip pads adjacent thereto by a first extending portion. The chip pads and the bond pads are arranged in an array. The chip pads are disposed at the center of the array and the bond pads are disposed around the chip pads. Each of the bond pads and at least one of the bond pads or one of the chip pads adjacent thereto each has a second extending portion formed therebetween and corresponding to each other. Every two of the second extending portions corresponding to each other are separated by a groove. The chip is mounted on a top surface of the chip pads and is electrically coupled to the bond pads.


Patent
ChipMOS Technologies | Date: 2015-03-20

A chip packaging structure includes an encapsulating material, plurality of first leads, plurality of second leads, a first chip, a second chip and an adhesion layer. The encapsulating material has a top package surface and a corresponding bottom package surface. Each first lead has a first inner lead portion and a first outer lead portion. The first chip is located on the first inner lead portion and electrically coupled to the first leads. Each second lead has a second inner lead portion and a second outer lead portion. The second chip is located on the second inner lead portion and electrically coupled to the second leads. The adhesion layer is located between the first leads and second leads so that the first leads and second leads are connected to each other.


Patent
ChipMOS Technologies | Date: 2014-11-25

A semiconductor package and manufacturing method thereof are disclosed. The semiconductor package includes a package carrier, a chip, a film, a first shielding metal plate and an encapsulating material. The package carrier has at least one conductive component. The chip has an active surface and a corresponding back surface. The back surface of the chip is attached to the package carrier. At least one contact point is disposed on the active surface and is electrically coupled to the conductive component by a wire. The film is disposed on the active surface and covers a portion of the wire. The first shielding metal plate is disposed on the film. The encapsulating material covers the chip, the wire, at least one portion of the package carrier, the film and at least one portion of the first shielding metal plate.

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