Hsinchu, Taiwan

ChipMOS Technologies

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Hsinchu, Taiwan
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A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.


Patent
ChipMOS Technologies | Date: 2015-06-03

A semiconductor structure includes a semiconductor device (100), a conductive pad (102) on the semiconductor device (100), and a Ag_(1-x)Y_(x) alloy bump (101) over the conductive pad (102). The Y of the Ag_(1-x)Y_(x) bump (101) comprises metals forming complete solid solution with Ag at arbitrary weight percentage (Au and/or Pd), and the x of the Ag_(1-x)Y_(x) alloy bump (101) is in a range of from about 0.005 to about 0.25. A difference between standard deviation and mean value of a grain size distribution of the Ag_(1-x)Y_(x) alloy bump (101) is in a range of from about 0.2 m to about 0.4 m. An average grain size of the Ag_(1-x)Y_(x) alloy bump (101) on a longitudinal cross sectional plane is in a range of from about 0.5 m to about 1.5 m. The alloy bump (101) is formed by electroplating.


Patent
ChipMOS Technologies | Date: 2016-08-18

A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated AuSn. alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling, with the electroplated AuSn alloy bump, wherein the electroplated AuSn alloy bump has a composition from about Au_(0.35)Sn_(0.15 )to about Au_(0.75)Sn_(0.25 )in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating AuSn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by reflow operation or a thermal press operation.


Patent
ChipMOS Technologies | Date: 2015-03-09

A semiconductor package and manufacturing method thereof are disclosed. The semiconductor package includes a photosensitive conductive layer, a chip and an encapsulant. The photosensitive conductive layer includes at least one electrically conductive portion and at least one insulating portion. The chip is disposed on the photosensitive conduct layer and electrically coupled the least one electrically conductive portion. The encapsulant covers the chip and the photosensitive conductive layer.


Patent
ChipMOS Technologies | Date: 2016-06-20

A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.


Patent
ChipMOS Technologies | Date: 2015-03-12

A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip pad is connected to at least one of the chip pads adjacent thereto by a first extending portion. The chip pads and the bond pads are arranged in an array. The chip pads are disposed at the center of the array and the bond pads are disposed around the chip pads. Each of the bond pads and at least one of the bond pads or one of the chip pads adjacent thereto each has a second extending portion formed therebetween and corresponding to each other. Every two of the second extending portions corresponding to each other are separated by a groove. The chip is mounted on a top surface of the chip pads and is electrically coupled to the bond pads.


Patent
ChipMOS Technologies | Date: 2015-03-20

A chip packaging structure includes an encapsulating material, plurality of first leads, plurality of second leads, a first chip, a second chip and an adhesion layer. The encapsulating material has a top package surface and a corresponding bottom package surface. Each first lead has a first inner lead portion and a first outer lead portion. The first chip is located on the first inner lead portion and electrically coupled to the first leads. Each second lead has a second inner lead portion and a second outer lead portion. The second chip is located on the second inner lead portion and electrically coupled to the second leads. The adhesion layer is located between the first leads and second leads so that the first leads and second leads are connected to each other.


Patent
ChipMOS Technologies | Date: 2015-04-17

A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated AuSn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated AuSn alloy bump, wherein the electroplated AuSn alloy bump has a composition from about Au_(0.85)Sn_(0.15 )to about Au_(0.75)Sn_(0.25 )in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating AuSn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.


Patent
ChipMOS Technologies | Date: 2015-09-16

An electrochemical reactor includes an adjustable electric field shaping capability during electroplating. The electrochemical reactor includes a reservoir configured to retain an electrolytic solution; a cathode and an anode disposed in the reservoir to form electric field lines passing through the electrolytic solution. Either the cathode or the anode includes a workpiece holder. A shield attaches to the cathode or the anode without the workpiece holder. The shield includes a surface configured to block a portion of the electric field lines, and a conduit positioned on the surface and configured to concentrate the electric field lines within the conduit. The conduit includes a protruding portion including a height measured from the surface to a top surface of the conduit, and an aperture penetrating the protruding portion and passing through the surface. The aperture is configured to allow the electric field lines to pass through the conduit.


Patent
ChipMOS Technologies | Date: 2015-09-16

The present disclosure relates to a semiconductor structure, which includes a semiconductor substrate, an insulating layer and a plurality of wirings. The insulating layer is disposed on the semiconductor substrate. The plurality of wirings are disposed between the semiconductor substrate and the insulating layer. At least one wiring of the wirings includes a plurality of holes, and a total area of the holes is from 10% to 70% of a surface area of the at least one wiring.

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