Colonia Nicolas Bravo (Kilometro Noventa y Dos), Mexico
Colonia Nicolas Bravo (Kilometro Noventa y Dos), Mexico

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A method for filling, on a wafer, chip-level atomic clock absorption bubbles with a high-purity alkali metal. The method comprises: 1) forming a micro groove (102), an absorption bubble cavity groove and an accommodation cavity groove in a silicon wafer (101); 2) sealing an alkali metal compound (106) in an accommodation cavity (103) in the center of the wafer, and forming a vacuum environment in the wafer comprising a temporary flowing micro channel, an absorption bubble cavity and the alkali metal accommodation cavity (103); 3) implementing decomposition of the alkali metal compound to generate a rubidium or cesium metal in a needed amount, and vaporizing and volatilizing the metal; 4) solidifying and coagulating the gaseous alkali metal in the absorption bubble cavity (104); and 5) bending a glass sheet under the action of electrostatic force, eliminating the precast temporary flowing micro channel (108), and simultaneously sealing all absorption bubbles. By means of the method, the problems of high filling difficulty, complex process and the like caused by extremely high probability of oxidization of an alkali metal are solved, reaction impurities probably left in the absorption bubbles are eliminated, and all the absorption bubbles on the alkali metal wafer are filled at a time, and the method can be used for mass production of chip-level atomic clock bubbles.


Zhou G.,China Institute of Technology
Modern Tunnelling Technology | Year: 2013

The risk of damage caused by freezing is very common for tunnels in cold regions; the influencing factors in these circumstances are complex and there are many uncertainties. Based on broad research results combined with the Likert questionnaire survey, an index system for assessing the risk of frost damage was set up in order to analyze the mutual effects of various factors, calculate the overall weight of the secondary index using ANP, and identify the main risk sources. Using the fuzzy evaluation method, the experts' comments were addressed and the comprehensive scores of frost damage with overall weight were calculated. Using KunLun mountain tunnel as an experimental example, this paper asserts that the system has three characteristics, which are pertinence, objectivity, and feasibility, and proves that the system can effectively identify influential factors of frost damage. Using both ANP and the fuzzy comprehensive evaluation method it is possible to identify the main sources of the risk and to allow for the creation of an influence index, thereby providing theoretical evidence for effective risk management.


Patent
China Institute of Technology | Date: 2013-11-28

A layout design method is provided for generating capacitor arrays being described in four steps: first, the wiring mode of unit capacitors is defined allowing the wire being connected to the upper plate to parallel that to the lower one, second, a capacitor array layout is designed with capacitors being distributed in Mh lines, Mh is the maximum of capacitors lines, the line numbers of Class 1 to Class K capacitors are defined in the unilateral capacitor array, third, the wiring mode is set for capacitor array making sure the lengths of the wires to the upper and lower plates of unit capacitors are equal, at last, parasitic parameters are characterized in ways that verify the layout. A capacitor array is provided as well. By eliminating capacitance mismatching caused by parasitic capacitance, the method works to generate a well-matched capacitor array in an easy and efficient way.


Patent
China Institute of Technology | Date: 2014-05-05

A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.


A device structure is provided to reduce the leakage current of semiconductor devices with a floating buried layer (FBL), includes a substrate, a first epitaxial layer, a split floating buried layer, a second epitaxial layer, a doped trench, a protected device, a surface junction termination extension (S-JTE) and a scribe street. The device and the S-JTE are designed at the second epitaxial layer and the split floating buried layer at the joint of the first and second epitaxial layers. The doped trench is penetrated through the second epitaxial layer and connected to the split floating buried layer. The substrate, the first and second epitaxial layers feature the same typed doping which is opposite to that of split floating buried layer and doped trench.


Patent
China Institute of Technology | Date: 2014-04-02

A band-gap reference circuit includes a proportioned current generating circuit, a startup circuit, a current mirror circuit, a high-order temperature compensation generating circuit and a reference generating circuit. The proportioned current generating circuit is configured to generate a current in direct proportion to the absolute temperature. The startup circuit is configured to start up the proportioned current generating circuit when the startup circuit is power on. The current mirror circuit is configured to reproduce a current which is the same as the current in direct proportion to the absolute temperature. The high-order temperature compensation generating circuit is configured to generate a compensation current of high-order temperature coefficient. The reference generating circuit is configured to add the voltage which is generated by the proportioned current generating circuit to a voltage of negative temperature coefficient according to a certain proportion, and output a reference voltage of zero temperature coefficient.


Patent
China Institute of Technology | Date: 2013-01-02

A measuring device for the short-wavelength X-ray diffraction for test samples or work pieces made of lower-atomic-number crystalline and a method thereof are disclosed in the present invention. The measuring device comprises: an X-ray tube, an incident diaphragm, a table, a position-restricting receiving slit for a position-restricted part of a measured sample or work piece, a goniometer, a detector and an energy analyzer, the said X-ray tube and detector are arranged in the two sides of the table on which the sample or work pieces is located, the detector is intended to receive the transmitted diffracted ray. With the short-wavelength X-ray diffraction transmission method in the present invention, X-ray diffracting patterns at different depths and different parts of a thicker test sample or work piece made of crystalline material and their distribution can be obtained without destructing the test sample or work piece, and processed by a computer to obtain phase, residual stress, etc. of any part and its distribution in the measured sample or work piece. The present invention has the advantages of easy operation, shorter detection time, and high trueness and reliability of the measured diffracting pattern.


Patent
China Institute of Technology | Date: 2013-04-15

A high-speed sampling front-end circuit is presented that includes a MDAC sampling network, a reference voltage generator circuit, a comparator array, an operational amplifier, an output short-circuit switch, an adjustable clock duty cycle stabilizer, a status control module and a feedback control module. The circuit features low power, high sampling rate and high input bandwidth of sampling network. The time constant of the MDAC sampling network and the comparator array is precisely matched one another to improve input bandwidth of the sampling network. Sampling capacitors are designed as feedback capacitors and DAC calculation capacitors, thereby the operational amplifier doubles feedback coefficient and features 50% bandwidth and 50% power. The cycle stabilizer is adopted to shorten sampling time and extend amplification phase to greatly improve sampling rate. One input reference voltage tends to simplify the design of the reference voltage generator circuit. The circuit has wide applications in pipelined A/D converters.


Patent
China Institute of Technology | Date: 2015-01-28

A dither circuit for high-resolution analog-to-digital converters(ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.


Patent
China Institute of Technology | Date: 2012-11-19

A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits transconductance and output impedance resulting from input signals variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.

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