Chartered Semiconductor was created in 1987, as a venture that included Singapore Technologies Engineering Ltd. Yet, it was not until 2000, that ST Engineering , a wholly owned subsidiary of Temasek Holdings wholly acquired Chartered.Prior to 2010, Chartered Semiconductor Manufacturing was the world's third largest dedicated independent semiconductor foundry, with its headquarters and main operations located in the Woodlands Industrial Park, Kranji Singapore. The company was listed on the Singapore Exchange under the trading symbol of CHARTERED, as well as on NASDAQ , until its buyout. Wikipedia.
Ibm, Samsung and Chartered Semiconductor Manufacturing Ltd. | Date: 2010-03-22
The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
Ibm, Freescale Semiconductor, Infineon Technologies and Chartered Semiconductor Manufacturing Ltd. | Date: 2010-01-14
An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
Chartered Semiconductor Manufacturing Ltd. and Ibm | Date: 2010-08-09
The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
Chartered Semiconductor Manufacturing Ltd. | Date: 2010-01-28
A method of making a mask is disclosed. The method includes providing a first and a second mask layers and disposing a first phase shift region on the first mask layer. A second phase shift region is disposed on the second mask layer, wherein the first and second phase shift regions are out of phase. A continuous unit cell is formed in the first phase shift region. The unit cell comprises a center section and distinct extension sections. The extension sections are contiguous to and extend outwards from the center section. The distinct extension sections have a same width as the center section. The second phase shift region is adjacent to the unit cell in the first phase shift region.
Chartered Semiconductor Manufacturing Ltd. | Date: 2010-05-20
An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization.
Chartered Semiconductor Manufacturing Ltd. | Date: 2010-01-29
A method for forming a semiconductor device is presented. The method includes providing a substrate having a photoresist thereon and transmitting a light source through a mask having a pattern onto the photoresist. The mask comprises a mask substrate having first, second and third regions, the third region is disposed between the first and second regions. The mask also includes a light reducing layer over the mask substrate having a first opening over the first region and a second opening over the second region. The first and second openings have layer sidewalls. The sidewalls of the light reducing layer are slanted at an angle less than 90 degrees with the plane of a top surface of the mask substrate. The method also includes developing the photoresist to transfer the pattern of the mask to the photoresist.
Chartered Semiconductor Manufacturing Ltd. | Date: 2010-01-04
A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
Chartered Semiconductor Manufacturing Ltd. | Date: 2011-09-26
An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate.
Chartered Semiconductor Manufacturing Ltd. | Date: 2011-07-26
Methods (and semiconductor substrates produced therefrom) of fabricating (n1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n1 SDOI substrates.
Chartered Semiconductor Manufacturing Ltd. | Date: 2010-01-25
A method of forming an integrated circuit is disclosed. The method includes providing a substrate and forming on the substrate a shield structure comprising a shield member and a ground strap. The shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion.