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Chang C.-C.,National Central University | Shen P.-K.,National Central University | Chen C.-T.,National Central University | Hsiao H.-L.,National Central University | And 3 more authors.
Optics Letters | Year: 2012

A silicon on insulator (SOI)-based trapezoidal waveguide with a 45° reflector for noncoplanar optical interconnect is demonstrated. The proposed waveguide is fabricated on an orientation-defined (100) SOI substrate by using a singlestep anisotropic wet-etching process. The optical performances of proposed waveguides are numerically and experimentally studied. Transmittance of ?4.51 dB, alignment tolerance of ±20 μm, cross talk of ?53 dB, and propagation loss of ?0.404 dB?cm are achieved The proposed waveguide would be a basic element and suitable for the future intrachip optical interconnects. © 2012 Optical Society of America. Source


Shen P.-K.,National Central University | Chen C.-T.,National Central University | Chang C.-C.,National Central University | Hsiao H.-L.,National Central University | And 6 more authors.
Optics Express | Year: 2012

An optical interconnect transmitter based on guided-wave silicon optical bench is demonstrated. The guided-wave silicon optical bench (GW-SiOB) is developed on a silicon-on-insulator (SOI) substrate. The three-dimensional guided-wave optical paths on the silicon optical bench are realized using trapezoidal waveguides monolithically integrated with 45° micro-reflectors. Such three-dimensional guided-w ave optical paths of SiOB would simplify and shrink the intra-chip optical interconnects located on a SOI substrate. The clearly open eye patterns operated at a data rate of 5 Gbps verifies the proposed GW-SiOB is suitable for intra-chip optical interconnects. © 2012 Optical Society of America. Source


Patent
Centera Photonics Inc. | Date: 2012-05-15

A wafer-level process for fabricating a plurality of photoelectric modules is provided. The wafer-level process includes at least following procedures. Firstly, a wafer including a plurality of chips arranged in an array is provided. Next, a plurality of photoelectric devices are mounted on the chips. Next, a cover plate including a plurality of covering units arranged in an array is provided. Next, a plurality of light guiding mediums are formed over the cover plate. Next, the cover plate is bonded with the wafer by an adhesive, wherein each of the covering units covers and bonds with one of the chips, and the light guiding mediums are sandwiched between the cover plate and the wafer. Then, the wafer and the cover plate are diced to obtain the plurality of photoelectric modules.


Patent
Centera Photonics Inc. | Date: 2015-05-20

A detachable package structure that includes an assembly substrate, a first semiconductor substrate, a second semiconductor substrate, and a combination element is provided. The first semiconductor substrate is disposed on the assembly substrate and has a first alignment portion. The second semiconductor substrate has a second alignment portion. The combination element allows the first semiconductor substrate and the second semiconductor substrate to be detachably combined together, such that the first alignment portion and the second alignment portion are aligned and combined.


Patent
Centera Photonics Inc. | Date: 2012-03-18

An optical electrical module includes a first substrate, a second substrate, a bearing portion and at least one optical electrical element. The second substrate is combined with the first substrate and has a reflective surface facing to the first substrate. The bearing portion is disposed between the first substrate and the second substrate to limit at least one light guide element. The optical electrical element is disposed on a surface of the first substrate facing to the reflective surface and faces to the reflective surface. The optical electrical element is configured for providing or receiving light signals. The reflective surface and the light guide element are disposed on an optical path of the light signals.

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