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Bentoutou Y.,Center for Space Technology
World Academy of Science, Engineering and Technology | Year: 2011

On-board Error Detection and Correction (EDAC) devices aim to secure data transmitted between the central processing unit (CPU) of a satellite onboard computer and its local memory. This paper presents a comparison of the performance of four low complexity EDAC techniques for application in Random Access Memories (RAMs) on-board small satellites. The performance of a newly proposed EDAC architecture is measured and compared with three different EDAC strategies, using the same FPGA technology. A statistical analysis of single-event upset (SEU) and multiple-bit upset (MBU) activity in commercial memories onboard Alsat-1 is given for a period of 8 years. Source


Bentoutou Y.,Center for Space Technology
World Academy of Science, Engineering and Technology | Year: 2010

Memory Errors Detection and Correction aim to secure the transaction of data between the central processing unit of a satellite onboard computer and its local memory. In this paper, the application of a double-bit error detection and correction method is described and implemented in Field Programmable Gate Array (FPGA) technology. The performance of the proposed EDAC method is measured and compared with two different EDAC devices, using the same FPGA technology. Statistical analysis of single-event upset (SEU) and multiple-bit upset (MBU) activity in commercial memories onboard the first Algerian microsatellite Alsat-1 is given. Source


Bentoutou Y.,Center for Space Technology | Djaifri M.,Center for Space Technology | Si-Mohammed A.M.,Center for Space Technology
Acta Astronautica | Year: 2010

This paper presents the in-orbit observations of single event upset (SEU) and multiple bit upset (MBU) activity in the commercial random access memories (RAM) onboard the first Algerian microsatellite Alsat-1. The application of the quasi-cyclic codes for double-bit error detection and correction in commercial memories for use onboard Alsat-1 is presented. The performance of the proposed quasi-cyclic codec is measured and compared with two different error detection and correction (EDAC) devices, using the same FPGA technology. It is shown that such a technique is very efficient to detect and correct double bit errors. The results show that a fast and accurate data decoding is achieved and that the algorithm is robust, which makes it applicable in low earth orbits. © 2009 Elsevier Ltd. All rights reserved. Source

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