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Elshamy M.,Cairo University | Mostafa H.,Center for Nanoelectronics and Devices | Said M.S.,Cairo University
ICET 2014 - 2nd International Conference on Engineering and Technology | Year: 2015

To achieve high data density with low power consumption, technology migration into nano and molecular scales have been proposed. Discovery of the memristor has enabled the realization of denser nano-scale logic and memory systems. This is due to the memristor distinctive characteristics such as storing the historic state of the current passing through it, nano-scale device, and low power consumption. This work describes the design considerations of using a memristor in realization of a memory cell. Based on this analysis, a new read/write circuit is proposed and verified using a simulation tool. © 2014 IEEE. Source


Mostafa H.,Cairo University | Ismail Y.I.,Center for Nanoelectronics and Devices
ICET 2014 - 2nd International Conference on Engineering and Technology | Year: 2015

Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, an analytical model for the timing jitter and skew due to noise and process variations, respectively, is proposed for the VTC circuit. The derived model is verified and compared to Monte Carlo simulations and Eldo transient noise simulations by using industrial 65-nm CMOS technology. This paper provides new design insights such as the impact of timing jitter/skew on the ADC resolution and the maximum input voltage frequency. © 2014 IEEE. Source


Elshamy M.,Cairo University | Mostafa H.,Center for Nanoelectronics and Devices | Said M.S.,Cairo University
ICET 2014 - 2nd International Conference on Engineering and Technology | Year: 2015

The recently found Memristor is a potential candidate for the next-generation memory because of its nano-scale and non-volatile advantages. In this paper, a new Read/Write circuit design is proposed based on the Memristor as a memory element. The proposed circuit exhibits low power consumption, short delay time, and occupying less layout area. In addition, the proposed circuit has the advantage of non-destructive successive reading cycles capability. © 2014 IEEE. Source


Mostafa H.,Cairo University | Ismail Y.I.,Center for Nanoelectronics and Devices
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems | Year: 2013

Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, a novel VTC circuit is proposed which achieves high linearity and large dynamic analog input range. This new VTC circuit can be used in a 5 bit time-based ADC with no sample and hold circuit for analog input frequencies up to 4 GHz. © 2013 IEEE. Source


Mostafa H.,Cairo University | Ismail Y.I.,Center for Nanoelectronics and Devices
Canadian Conference on Electrical and Computer Engineering | Year: 2014

Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, an analytical model for the timing jitter and skew due to noise and process variations, respectively, is proposed for the VTC circuit. The derived model is verified and compared to Monte Carlo simulations and Eldo transient noise simulations by using industrial 65-nm CMOS technology. This paper shows how the timing jitter/skew can be reduced by using circuit design knobs such as the supply voltage and the load capacitance. © 2014 IEEE. Source

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