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Ashraf M.,Cairo University | Mostafa H.,Cairo University | Mostafa H.,Center for Nanoelectronics and Devices | El-Adawy A.A.,Cairo University
Proceedings of the International Conference on Microelectronics, ICM | Year: 2017

Nowadays, brain scientific research progress depends on signal compression at high spatial resolutions, for efficient storage and low-rate transmission through wireless connection to outside world. So that neural data compression at the implant site is necessary in order to conform with the wireless rates restrictions. In this paper, the high spatial correlation is utilized to increase the data compression ratio. Then we investigate and compare three different proposed low-power image compression algorithms based on discrete cosine transform (DCT) and discrete wavelet transform (DWT) to provide the best trade-off between hardware complexity and compression performance. Hence, we conclude that Adaptive 2D-DWT algorithm is a promising solution for low-power implantable devices. © 2016 IEEE.


Belal E.,Cairo University | Mostafa H.,Cairo University | Ismail Y.,Center for Nanoelectronics and Devices | Said M.S.,Cairo University
Proceedings of the International Conference on Microelectronics, ICM | Year: 2017

This paper presents a low voltage AC/DC converter using a voltage multiplier circuit for energy harvesting applications where a low voltage AC waveform used to charge a battery. The circuit rectified and boosted the AC input voltages in the range of 0.5-4 V and 40-150 Hz to a DC voltage in the range of 0.8-12 V. A maximum power efficiency of 71% achieved for AC amplitude 1.5 V with temperature measurements between-40 to +50 ° C. The proposed circuit fabricated using TSMC 130nm CMOS technology with an active area of 0.249 mm. © 2016 IEEE.


Alsenwi M.,Cairo University | Ismail T.,Cairo University | Mostafa H.,Cairo University | Mostafa H.,Center for Nanoelectronics and Devices
Proceedings of the International Conference on Microelectronics, ICM | Year: 2017

Long recording time, large number of electrodes, and a high sampling rate together produce a great data size of Electroencephalography (EEG). Therefore, more bandwidth and space are required for efficient data transmission and storing. So, EEG data compression is a very important problem in order to transmit EEG data efficiently with fewer bandwidth and storing it in a less space. In this paper, We use the Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) which are lossy compression methods in order to convert the randomness EEG data to high redundancy data. Therefore, adding a lossless compression algorithm after the lossy compression is a good idea to get a high compression ratio without any distortion in the signal. Here, we use Run Length Encoding (RLE) and Arithmetic Encoding which are lossless compression methods. Total times for compression and reconstruction (T), Compression Ratio (CR), Root Mean Square Error (RMSE), and Structural Similarity Index (SSIM) are evaluated in order to check the effectiveness of the proposed system. © 2016 IEEE.


Elshamy M.,Cairo University | Mostafa H.,Center for Nanoelectronics and Devices | Said M.S.,Cairo University
ICET 2014 - 2nd International Conference on Engineering and Technology | Year: 2015

The recently found Memristor is a potential candidate for the next-generation memory because of its nano-scale and non-volatile advantages. In this paper, a new Read/Write circuit design is proposed based on the Memristor as a memory element. The proposed circuit exhibits low power consumption, short delay time, and occupying less layout area. In addition, the proposed circuit has the advantage of non-destructive successive reading cycles capability. © 2014 IEEE.


Mostafa H.,Cairo University | Ismail Y.I.,Center for Nanoelectronics and Devices
ICET 2014 - 2nd International Conference on Engineering and Technology | Year: 2015

Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, an analytical model for the timing jitter and skew due to noise and process variations, respectively, is proposed for the VTC circuit. The derived model is verified and compared to Monte Carlo simulations and Eldo transient noise simulations by using industrial 65-nm CMOS technology. This paper provides new design insights such as the impact of timing jitter/skew on the ADC resolution and the maximum input voltage frequency. © 2014 IEEE.


El-Bayoumi A.,Cairo University | Mostafa H.,Center for Nanoelectronics and Devices | Soliman A.M.,Cairo University
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2015

Time-Based Analog-to-Digital Converter (ADC), at scaled CMOS technology, plays a major role in designing Software Defined Radio (SDR) receivers as it manifests higher speed and lower power than conventional ADCs. Time-Based ADC includes a Voltage-to-Time converter (VTC) which converts the input voltage into a pulse delay, and a Time-to-Digital Converter which converts the pulse delay into a digital word. In this paper, a novel design of a differential VTC circuit is proposed which reports wider dynamic range and higher sensitivity than previously published VTC circuits in TSMC 65nm CMOS technology, with a supply voltage of 1.2V. This new VTC circuit operates with no sample and hold circuit for analog input frequencies up to 2.5 GHz with a linearity error of 3%. © 2015 IEEE.


Mostafa H.,Cairo University | Mostafa H.,Center for Nanoelectronics and Devices | Ismail Y.,Center for Nanoelectronics and Devices
IEEE Transactions on Semiconductor Manufacturing | Year: 2016

The missing fourth passive element, predicted by L. Chua and denoted by memristor, has recently been in the research focus since its titanium dioxide thin film realization is reported by HP. Following that, the spintronic memristor, which is based on the magnetic tunneling junction, is presented as an alternative to the thin film memristor. The nano-scale geometry size of the memristor makes it hard to control its dimensions due to the process variation resulting from the fabrication process. This process variation results in yield degradation in the spintronic memristor-based memory arrays. This yield degradation is more significant when the spintronic memristor is utilized as a multi-valued memory elements. In this paper, the impact of the process variation on the spintronic memristor-based memory yield is discussed for the 1-bit, 2-bit, and n-bit memory element. Moreover, two approaches are introduced to enhance the memory yield. © 2016 IEEE.


Mostafa H.,Cairo University | Ismail Y.I.,Center for Nanoelectronics and Devices
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems | Year: 2013

Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, a novel VTC circuit is proposed which achieves high linearity and large dynamic analog input range. This new VTC circuit can be used in a 5 bit time-based ADC with no sample and hold circuit for analog input frequencies up to 4 GHz. © 2013 IEEE.


Mostafa H.,Cairo University | Ismail Y.I.,Center for Nanoelectronics and Devices
Canadian Conference on Electrical and Computer Engineering | Year: 2014

Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, an analytical model for the timing jitter and skew due to noise and process variations, respectively, is proposed for the VTC circuit. The derived model is verified and compared to Monte Carlo simulations and Eldo transient noise simulations by using industrial 65-nm CMOS technology. This paper shows how the timing jitter/skew can be reduced by using circuit design knobs such as the supply voltage and the load capacitance. © 2014 IEEE.


Friedman J.S.,Northwestern University | Rangaraju N.,Northwestern University | Ismail Y.I.,Center for Nanoelectronics and Devices | Wessels B.W.,Northwestern University
IEEE Transactions on Nanotechnology | Year: 2012

While most modern computing technologies utilize Si complementary metal-oxide-semiconductor (CMOS) transistors and the accompanying CMOS logic family, alternative devices and logic families exhibit significant performance advantages. Though heretofore impractical, diode logic allows for the execution of logic circuits that are faster, smaller, and dissipate less power than conventional architectures. In this paper, magnetoresistive semiconductor heterojunctions are used to produce the first complete logic family based solely on diodes. We utilize the diode magnetoresistance states to create a binary logic family based on high and low currents in which a full range of logic functions is executed. The diode is used as a switch by manipulating its magnetoresistance with current-carrying wires that generate magnetic fields. Using this device structure, we present basis logic elements and complex circuits consisting of as few as 10 of the devices required in their conventional CMOS counterparts. This diode logic family is therefore an intriguing potential replacement for CMOS technology as Si scaling reaches its inherent limits. © 2012 IEEE.

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