San Jose, CA, United States
San Jose, CA, United States

Cavium is a fabless semiconductor company based in San Jose, California specializing in ARM-based and MIPS-based network, video and security processors and SoCs. Cavium offers processor and board level products targeting routers, switches, appliances, storage and servers.The company went public in May 2007 with about 175 employees. As of 2011, following numerous acquisitions, it had about 850 employees worldwide, of whom about 250 were located at company headquarters in San Jose. Wikipedia.

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A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.


Patent
Cavium | Date: 2017-04-27

A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.


According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.


A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.


A new approach is proposed that contemplates systems and methods to support a mechanism to offload IPSec/IKE processing of virtual machines (VMs) running on a host to an embedded networking device, which serves as a hardware accelerator for the VMs that need to have secured communication with a remote device/server over a network. By utilizing a plurality of its software and hardware features, the embedded networking device is configured to perform all offloaded IPSec operations on data packets transferred between the host and the remote device over the network as required for the secured communication before the data packets can be transmitted over the network. The embedded networking device, in effect, acts as a proxy on behalf of the VMs running on the host to perform the offloaded IPSec operations as well as serving as the network interface for the secured communication between the VMs and the remote device.


A new approach is proposed to offload of link aggregation from a host to a HBA in SRIOV mode. The HBA first creates one or more link aggregation offload engines each having one or more physical ports and to establish a first link between a VM running on the host and one of the link aggregation offload engines for network data transmission with the VM. Once a data packet is received from the VM over the first link, the link aggregation offload engine chooses a first physical port based on its link aggregation method and establish a second link with the chosen first physical port to transmit the packet out of the HBA. If the second link fails, the link aggregation offload engine then chooses a second physical ports and establish a third link with the chosen second physical port to transmit the packet out of the HBA device instead.


Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.


A new approach is proposed that contemplates systems and methods to support dynamic regression test generation for an IC design based upon coverage-based clustering of RTL modules in the design. First, coverage data for code coverage by a plurality of RTL modules in the IC design are collected and a plurality of clusters of related RTL modules of the IC design are generated based on statistical analysis of the collected coverage data and hierarchal information of the RTL modules. When changes are made to the RTL modules during the IC design process, a plurality of affected RTL modules are identified based on the clusters of the RTL modules and a plurality of regression tests are generated dynamically for these affected RTL modules based on their corresponding coverage data. The dynamically generated regression tests are then run to verify the changes made in the IC design.


A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.


Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ACK) bits received from a UE that are contained in a received sub-frame of symbols. The ACK bits are soft-combined using a plurality of scrambling sequences to generate a plurality of hypothetical soft-combined ACK bit streams. The method also includes receiving a parameter that identifies a selected scrambling sequence to be used. The method also includes decoding a selected hypothetical soft-combined ACK bit stream to generate a decoded ACK value, wherein the selected hypothetical soft-combined ACK bit stream is selected from the plurality of hypothetical soft-combined ACK bit streams based on the parameter.

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