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Patent
CAS Shanghai Institute of Microsystem and Information Technology | Date: 2014-02-21

A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeO


Patent
CAS Shanghai Institute of Microsystem and Information Technology | Date: 2012-12-27

The present invention relates to a metal element doped phase-change material in the field of micro-electronics technologies, specifically to an antimony-rich high-speed phase-change material used in a phase-change memory (PCRAM), a preparing method and an application thereof. The antimony-rich high-speed phase-change material used in a PCRAM has a chemical formula being A


Patent
CAS Shanghai Institute of Microsystem and Information Technology | Date: 2012-12-26

The present invention relates to an SbTeTi phase-change thin-film material applicable to a phase-change memory and preparation thereof. The SbTeTi phase-change memory material of the present invention is formed by doping an SbTe phase-change material with Ti, Ti forms bonds with both Sb and Te, and the SbTeTi phase-change memory material has a chemical formula Sb


Patent
CAS Shanghai Institute of Microsystem and Information Technology | Date: 2013-02-26

The present invention provides a variable area capacitive lateral acceleration sensor and a preparation method. The acceleration sensor at least includes: three-layer stack structure bonded by a first substrate, a second substrate and a third substrate which are electrically isolated with each other, wherein, the second substrate includes a movable seismic mass, a frame surrounded the movable seismic mass, a elastic beam connected to the movable seismic mass and the frame, a plurality of bar structure electrodes positioned on two surfaces of the movable seismic mass, an anti-overloading structure arranged on the movable seismic mass, etc.; the plurality of first bar structure electrodes on the first substrate and a plurality of second bar structure electrodes on one surface of the second substrate form capacitor structure, the plurality of third bar structure electrodes on the third substrate and a plurality of second bar structure electrodes on one surface of the second substrate form capacitor structure, and those two capacitor form differential sensitive capacitor structure. The present invention has the advantage of high sensitivity and good linearity, and different kinds of beam shapes may be designed as needed, to prepare capacitive acceleration sensors with different sensitivity, and the preparation has high flexibility.


Patent
CAS Shanghai Institute of Microsystem and Information Technology | Date: 2012-05-16

The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor. The preparation method for forming the semiconductor structure includes: preparing a global Ge on insulator substrate structure; preparing a group III-V semiconductor material layer on the Ge on insulator substrate structure; performing photolithography and etching for the first time to make a patterned window to the above of a Ge layer to form a recess; preparing a spacer in the recess; preparing a Ge film by selective epitaxial growth; performing a chemical mechanical polishing to obtain the heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material being coplanar; removing the spacer and a defective Ge layer part close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high-performance CMOS device including a Ge PMOS and a III-V NMOS by forming an MOS structure.

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