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Wen W.,Nanjing Southeast University | Wen W.,CAS Institute of Software
Proceedings - International Conference on Software Engineering | Year: 2012

During software development and maintenance stages, programmers have to frequently debug the software. One of the most difficult and complex tasks in the debugging activity is software fault localization. A commonly-used method to fix software fault is computing suspiciousness of program elements according to failed test executions and passed test executions. However, this technique does not give full consideration to dependences between program elements, thus its capacity for efficient fault localization is limited. Our research intends to introduce program slicing technique and statistical method which extracts dependencies between program elements and refines execution history, then builds program slicing spectra to rank suspicious elements by a statistical metric. We expect that our method will contribute directly to the improvement of the effectiveness and the accuracy of software fault localization and reduce the software development and maintenance effort and cost. © 2012 IEEE.


Sun Z.,CAS Institute of Automation | Zhang H.,CAS Institute of Software | Tan T.,CAS Institute of Automation | Wang J.,CAS Shanghai Institute of Technical Physics
IEEE Transactions on Pattern Analysis and Machine Intelligence | Year: 2014

Iris recognition as a reliable method for personal identification has been well-studied with the objective to assign the class label of each iris image to a unique subject. In contrast, iris image classification aims to classify an iris image to an application specific category, e.g., iris liveness detection (classification of genuine and fake iris images), race classification (e.g., classification of iris images of Asian and non-Asian subjects), coarse-to-fine iris identification (classification of all iris images in the central database into multiple categories). This paper proposes a general framework for iris image classification based on texture analysis. A novel texture pattern representation method called Hierarchical Visual Codebook (HVC) is proposed to encode the texture primitives of iris images. The proposed HVC method is an integration of two existing Bag-of-Words models, namely Vocabulary Tree (VT), and Locality-constrained Linear Coding (LLC). The HVC adopts a coarse-to-fine visual coding strategy and takes advantages of both VT and LLC for accurate and sparse representation of iris texture. Extensive experimental results demonstrate that the proposed iris image classification method achieves state-of-the-art performance for iris liveness detection, race classification, and coarse-to-fine iris identification. A comprehensive fake iris image database simulating four types of iris spoof attacks is developed as the benchmark for research of iris liveness detection. © 2013 IEEE.


Liao Q.,IBM | Shi L.,CAS Institute of Software
Proceedings of the ACM Conference on Computer Supported Cooperative Work, CSCW | Year: 2013

In this paper we report on a case study of rumor transmission during a nationwide scandal via China's most popular microblogging service, weibo.com. Specifically, we explore dynamics of the rumor discourse by characterizing different statement types and their evolution over time. We examine the roles that different user groups play in the rumor discussions. Through qualitative and statistical analyses, our results identify seven reaction patterns to rumors and their different development trends. We reveal a three-stage pattern of the change of leadership during the rumor discussions. By connecting social theories on rumor transmission to the large scale social platform, this paper offers insight into understanding rumor development in social media, as well as utilizing microblogging data for effectively detecting, analyzing and controlling public rumors. Copyright 2013 ACM.


Xia M.,CAS Institute of Software
Proceedings of the Annual ACM Symposium on Theory of Computing | Year: 2016

A holographic algorithm solves a problem in a domain of size n, by reducing it to counting perfect matchings in planar graphs. It may simulate a n-value variable by a bunch of t matchgate bits, which has 2t values. The transformation in the simulation can be expressed as a n × 2t matrix M, called the base of the holographic algorithm. We wonder whether more matchgate bits bring us more powerful holographic algorithms. In another word, whether we can solve the same original problem, with a collapsed base of size n × 2r, where r < t. Base collapse is discovered for small domain n = 2,3,4. For n = 3,4, the base collapse is proved under the condition that there is a full rank generator. We prove for any n, the base collapse to a r ≤ [log n], under some similar conditions. One of the conditions is that the original problem is defined by one symmetric function. In the proof, we utilize elementary matchgate transformations instead of matchgate identities. © 2016 ACM.


Liu F.,CAS Institute of Software | Wu C.,CAS Institute of Software
IEEE Transactions on Information Forensics and Security | Year: 2011

A visual cryptography scheme (VCS) is a kind of secret sharing scheme which allows the encoding of a secret image into ν shares distributed to $n$ participants. The beauty of such a scheme is that a set of qualified participants is able to recover the secret image without any cryptographic knowledge and computation devices. An extended visual cryptography scheme (EVCS) is a kind of VCS which consists of meaningful shares (compared to the random shares of traditional VCS). In this paper, we propose a construction of EVCS which is realized by embedding random shares into meaningful covering shares, and we call it the embedded EVCS. Experimental results compare some of the well-known EVCSs proposed in recent years systematically, and show that the proposed embedded EVCS has competitive visual quality compared with many of the well-known EVCSs in the literature. In addition, it has many specific advantages against these well-known EVCSs, respectively. © 2011 IEEE.


Wu W.,CAS Institute of Software | Zhang L.,CAS Institute of Software
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2011

In this paper, we propose a new lightweight block cipher called LBlock. Similar to many other lightweight block ciphers, the block size of LBlock is 64-bit and the key size is 80-bit. Our security evaluation shows that LBlock can achieve enough security margin against known attacks, such as differential cryptanalysis, linear cryptanalysis, impossible differential cryptanalysis and related-key attacks etc. Furthermore, LBlock can be implemented efficiently not only in hardware environments but also in software platforms such as 8-bit microcontroller. Our hardware implementation of LBlock requires about 1320 GE on 0.18 μm technology with a throughput of 200 Kbps at 100 KHz. The software implementation of LBlock on 8-bit microcontroller requires about 3955 clock cycles to encrypt a plaintext block. © 2011 Springer-Verlag Berlin Heidelberg.


Shen Y.-D.,CAS Institute of Software
IJCAI International Joint Conference on Artificial Intelligence | Year: 2011

[Fages, 1994] introduces the notion of well-supportedness as a key requirement for the semantics of normal logic programs and characterizes the standard answer set semantics in terms of the well-supportedness condition. With the property of well-supportedness, answer sets are guaranteed to be free of circular justifications. In this paper, we extend Fages' work to description logic programs (or DL-programs). We introduce two forms of well-supportedness for DL-programs. The first one defines weakly well-supported models that are free of circular justifications caused by positive literals in rule bodies. The second one defines strongly well-supported models that are free of circular justifications caused by either positive or negative literals. We then define two new answer set semantics for DL-programs and characterize them in terms of the weakly and strongly well-supported models, respectively. The first semantics is based on an extended Gelfond-Lifschitz transformation and defines weakly well-supported answer sets that are free of circular justifications for the class of DL-programs without negative dlatoms. The second semantics defines strongly wellsupported answer sets which are free of circular justifications for all DL-programs. We show that the existing answer set semantics for DL-programs, such as the weak answer set semantics, the strong answer set semantics, and the FLP-based answer set semantics, satisfy neither the weak nor the strong well-supportedness condition, even for DL-programs without negative dl-atoms. This explains why their answer sets incur circular justifications.


Barmpalias G.,CAS Institute of Software
Information and Computation | Year: 2013

We show that there are Turing complete computably enumerable sets of arbitrarily low nontrivial initial segment prefix-free complexity. In particular, given any computably enumerable set A with nontrivial prefix-free initial segment complexity, there exists a Turing complete computably enumerable set B with complexity strictly less than the complexity of A. On the other hand it is known that sets with trivial initial segment prefix-free complexity are not Turing complete. Moreover we give a generalization of this result for any finite collection of computably enumerable sets Ai, i


Patent
CAS Institute of Software | Date: 2012-10-19

The present invention discloses a LPC2468-based MVB-WTB gateway and associated operating methods in the field of train communications. The disclosed network gateway includes a MVB network card and a WTB network card. The WTB network card includes WTB-ARM and a WTB-FPGA module. The MVB network card includes MVB-ARM and MVB-FPGA module. The WTB-ARM module uses a LPC2468 processor to analyze data in the network layer and the data link layer based on gateway protocol. The WTB-FPGA module allows WTB to exchange data with other networks gateways, as well as between the WTB and MVB. The MVB-ARM module is responsible for executing protocols on the network cards. Via data communications on MVB, the MVB-FPGA module collects the process and message data of the MVB equipment, and exchange communication data between WTB within a network gateway. The present invention can increase speed and enhance reliability for communications between gateways.


Patent
CAS Institute of Software | Date: 2012-10-19

The present invention relates to the field of communications on rail trains. A PicoBlaze-based MVB controller includes a pMVB controller, a traffic memory, an ARM adapter, and a bus arbiter. The pMVB controller, the traffic memory, ARM adapter, and the bus arbiter are connected to an external bus BUS1. The pMVB controller is connected to the traffic memory. The ARM adapter is connected to an external ARM processor and the bus arbiter. The traffic memory can store network communication data and input control information, and send them to the pMVB controller. The pMVB controller responds to the control information, and sends the communication data, and after it is encoded, to the MVB bus via the external bus BUS1. The pMVB controller also decodes data received from the pMVB bus and triggers an interrupt. The bus arbiter is responsible for bus arbitration in accordance with the instructions from the pMVB controller.

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