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Patent
CAS Institute of Semiconductors | Date: 2013-11-26

The present disclosure involves a GaN-based Schottky diode rectifier and a method of manufacturing the same. The GaN-based Schottky diode rectifier includes: a substrate, on which a GaN intrinsic layer and a barrier layer are grown in turn; a p-type two-dimension electron gas depletion layer located on an upper surface of the barrier layer; a cathode electrode located at a position on the upper surface of the barrier layer where is different from the position where the p-type two-dimension electron gas depletion layer is formed; and an anode electrode including a first part and a second part electrically connected to each other.


Patent
CAS Institute of Semiconductors | Date: 2014-06-26

The present disclosure discloses a wireless radio-frequency transmission apparatus, comprising: a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator, wherein the twin voltage-controlled oscillator comprises a first voltage-controlled oscillator and a second voltage-controlled oscillator which are of the same structure, wherein when the twin voltage-controlled oscillator is in a reception mode, the first voltage-controlled oscillator and the second voltage-controlled oscillator are coupled to each other to form a quadrature voltage-controlled oscillator, and the quadrature voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop to generate quadrature carriers for receiving information; and when the twin voltage-controlled oscillator is in a transmission mode, the first voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop, and the second voltage-controlled oscillator is used for performing frequency modulation on transmitted data. The present disclosure can maintain a carrier frequency to be stable during high data rate transmission, and have a relatively short locking time of frequency hopping.


Patent
CAS Institute of Semiconductors | Date: 2016-12-21

A multi-band channel encrypting switch control device is provided. The device comprises a transmission part and a receiving part. The transmission part comprises: a first controller to store a secret key and to send a digital signal; an encrypting unit to encrypt the digital signal; a multi-band transmitter to select a plurality of wavebands to transmit the encrypted signal on the plurality of wavebands under control of the secret key; and a switch. The receiving part comprises: a multi-band detector to receive the encrypted signal transmitted on the plurality of wavebands; a decrypting unit to decrypt the encrypted signal; and a second controller to store the secret key and to decide whether or not to issue a switch signal by processing the signal and making decisions using the process result. A transmission device, a receiving device, and a control method are also provided. The encrypted data is transmitted via different channels to reduce possibility of signal interception during the transmission, thereby improving security significantly.


Patent
CAS Institute of Semiconductors | Date: 2014-06-24

The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (102), a loop filter (103) parameter, a multi-path voltage-controlled oscillator (104) and a first multiplexer (105) corresponding thereto, a five-stage-division-by-two frequency division link (109) and a corresponding second multiplexer (110) and third multiplexer (112), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.


Wu Z.,CAS Institute of Semiconductors
Applied Physics Letters | Year: 2011

We investigate theoretically the transmission properties through a p-n-p junction on graphene. Here, we show that the electronic transport property presents deep analogies with light propagation. It originates from the similarity between the linear spectra of the Dirac fermions and photons that obey the Maxwell's equations. We demonstrate that the p-n-p channel acts as an electronic fiber in which electrons propagate along the channel without dissipation. © 2011 American Institute of Physics.


Patent
CAS Institute of Semiconductors | Date: 2016-08-24

The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.


The present invention discloses a method of forming a polygon-sectional rodlike ingot having an orientation marker or rounded corners, a rodlike ingot and a sheet substrate so formed. The method comprises: selecting one of sides of the polygon-sectional rodlike ingot that is parallel to an axial direction thereof as a first feature of a surface orientation marker; forming a minisize notch, which is parallel to an edge, in the one of sides selected as the first feature in the axial direction of the rodlike ingot, as a second feature of the orientation marker; and processing the rodlike ingot to form rounded corners. The sheet substrate is obtained by cutting the rodlike ingot.


Patent
CAS Institute of Semiconductors | Date: 2014-03-21

A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the samples GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO_(2 )layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO_(2 )layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO_(2 )layer on the nMOSFET structure; performing a CMOS process.


Patent
CAS Institute of Semiconductors | Date: 2014-01-03

The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.


Patent
CAS Institute of Semiconductors | Date: 2013-08-27

A method for manufacturing a distributed feedback laser array includes: forming a bottom separate confinement layer on a substrate; forming a quantum-well layer on the bottom separate confinement layer; forming a selective-area epitaxial dielectric mask pattern on the quantum-well layer; forming a top separate confinement layer on the quantum-well layer through selective-area epitaxial growth using the selective-area epitaxial dielectric mask pattern, the top separate confinement layer having different thicknesses for different laser units; removing the selective-area epitaxial dielectric mask pattern; forming an optical grating on the top separate confinement layer; and growing a contact layer on the optical grating. The present disclosure achieves different emission wavelengths for different laser units without significantly affect emission performance of the quantum-well material.

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