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Patent
CAS Institute of Semiconductors | Date: 2013-11-26

The present disclosure involves a GaN-based Schottky diode rectifier and a method of manufacturing the same. The GaN-based Schottky diode rectifier includes: a substrate, on which a GaN intrinsic layer and a barrier layer are grown in turn; a p-type two-dimension electron gas depletion layer located on an upper surface of the barrier layer; a cathode electrode located at a position on the upper surface of the barrier layer where is different from the position where the p-type two-dimension electron gas depletion layer is formed; and an anode electrode including a first part and a second part electrically connected to each other.


Pei Y.,CAS Institute of Semiconductors
Physica B: Condensed Matter | Year: 2012

The influences of strain to the energetic and electronic properties of graphdiyne are investigated based on first-principles calculations. The elastic parameters of graphdiyne are determined by total energy calculation. Compared to graphyne, graphdiyne is softer because it has less C-C bonds. Moreover, the band gap of graphdiyne is tunable under uniform strain. It monotonously increases with increasing strain value, which originates from the decreased orbital overlap between C atoms when strain increases. © © 2012 Elsevier B.V. All rights reserved.


Wu Z.,CAS Institute of Semiconductors
Applied Physics Letters | Year: 2011

We investigate theoretically the transmission properties through a p-n-p junction on graphene. Here, we show that the electronic transport property presents deep analogies with light propagation. It originates from the similarity between the linear spectra of the Dirac fermions and photons that obey the Maxwell's equations. We demonstrate that the p-n-p channel acts as an electronic fiber in which electrons propagate along the channel without dissipation. © 2011 American Institute of Physics.


Ge/Si heterojunction light emitting diodes with 20-bilayers undoped or phosphorus in situ doped GeSi islands were fabricated on n(+)(-)Si(001) substrates by ultrahigh vacuum chemical vapor deposition (UHV-CVD). Enhanced room temperature photoluminescence (PL) and electroluminescence (EL) around 1.5 μm were observed from the devices with phosphorus-doped GeSi islands. Theoretical calculations indicated that the emission is from the radiative recombination in GeSi islands. The intensity enhancement of PL and EL is attributed to the sufficient supply of electrons in active layer for radiative recombination.


The disclosure provides a system and method for multi-functional online testing of semiconductor light-emitting devices or modules. The system comprises an electrical characteristic generating and testing equipment, one or more optical characteristic detecting and controlling equipments, an optical signal processing and analyzing equipment, one or more thermal characteristic detecting equipments, a central monitoring and processing computer, a multi-channel integrated drive controlling equipment, one or more multi-stress accelerated degradation controlling equipments, and one or more load boards. The present disclosure enables in-situ online monitoring and testing under accelerated degradation in a multi-stress accelerated degradation environment.


Patent
CAS Institute of Semiconductors | Date: 2016-08-24

The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.


The present invention discloses a method of forming a polygon-sectional rodlike ingot having an orientation marker or rounded corners, a rodlike ingot and a sheet substrate so formed. The method comprises: selecting one of sides of the polygon-sectional rodlike ingot that is parallel to an axial direction thereof as a first feature of a surface orientation marker; forming a minisize notch, which is parallel to an edge, in the one of sides selected as the first feature in the axial direction of the rodlike ingot, as a second feature of the orientation marker; and processing the rodlike ingot to form rounded corners. The sheet substrate is obtained by cutting the rodlike ingot.


Patent
CAS Institute of Semiconductors | Date: 2014-03-21

A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the samples GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO_(2 )layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO_(2 )layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO_(2 )layer on the nMOSFET structure; performing a CMOS process.


Patent
CAS Institute of Semiconductors | Date: 2014-01-03

The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.


Patent
CAS Institute of Semiconductors | Date: 2013-08-27

A method for manufacturing a distributed feedback laser array includes: forming a bottom separate confinement layer on a substrate; forming a quantum-well layer on the bottom separate confinement layer; forming a selective-area epitaxial dielectric mask pattern on the quantum-well layer; forming a top separate confinement layer on the quantum-well layer through selective-area epitaxial growth using the selective-area epitaxial dielectric mask pattern, the top separate confinement layer having different thicknesses for different laser units; removing the selective-area epitaxial dielectric mask pattern; forming an optical grating on the top separate confinement layer; and growing a contact layer on the optical grating. The present disclosure achieves different emission wavelengths for different laser units without significantly affect emission performance of the quantum-well material.

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