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Patent
CAS Institute of Microelectronics | Date: 2015-07-22

A method for collecting a signal with a frequency lower than a Nyquist frequency includes, by a data transmitting end, selecting a suitable transformation base matrix for an input signal, deriving a sparse representation of the signal using the transformation base matrix to determine a sparsity of the signal, calculating a number M of compressive sampling operations according to the sparsity, sampling the signal with f


Patent
CAS Institute of Microelectronics | Date: 2015-05-29

A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.


Patent
CAS Institute of Microelectronics | Date: 2015-04-28

A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer thereon in the gate trench; forming a first tungsten (W) layer on a surface of the metal gate layer, and forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions; and filling with W through an atomic layer deposition (ALD) process. The blocking layer prevents ions in the precursors from aggregating on an interface and penetrating into the metal gate layer and the gate dielectric layer. At the same time, adhesion of W is enhanced, a process window of W during planarization is increased, reliability of the device is improved and the gate resistance is further reduced.


The present disclosure provides a method for preparing compound semiconductor sensitive film based on a displacement reaction-thermal oxidation method, the method comprising: growing a layer of Zn on a high temperature-resistant substrate; submerging the substrate on which the layer of Zn has been grown into ionic solution of soluble salt of Cu, such that Cu ions in the solution are displaced so as to separate Cu nano-particles out on a surface of the layer of Zn; and performing a thermal oxidation process on the layer of Zn to whose surface Cu nano-particles are adhered, such that the Cu nano-particles are oxidized into CuO nano-particles, so as to obtain a ZnO gas sensitive film that is doped with CuO nano-particles. The above preparing method has the following advantages: good filming quality, simplified preparation process, low cost and easy to control.


Patent
CAS Institute of Microelectronics | Date: 2015-04-16

Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

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