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Patent
CAS Institute of Microelectronics | Date: 2014-07-10

A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.


Patent
CAS Institute of Microelectronics | Date: 2014-08-01

A method for manufacturing a FinFET device, including providing a substrate; implementing a source/drain doping on the substrate; etching the doped substrate to form a source region and a drain region; forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel. The fin and the gate are formed after the source/drain doping is implemented on the substrate, so that the source/drain doping is done as a doping for a planar device, which ensures the quality of the source/drain coping and improves the property of the FinFET device.


Patent
CAS Institute of Microelectronics | Date: 2015-03-19

The present disclosure provides a method of manufacturing a semiconductor device having silicon nitride with a tensile stress, the method comprising: c1) introducing and pre-stabilizing NH_(3 )gas and N_(2 )gas; c2) introducing silane; c3) igniting the gases by a radio-frequency source; c4) depositing SiN; and c5) processing the SiN by using a nitrogen ion implantation. According to the present disclosure, the nitrogen content in the SiN film can be enhanced by the nitrogen ion implantation and impinging, thereby increasing the density of the film. In this way, the acid resistance of the SiN with tensile stress is enhanced, so that the SiN with tensile stress may be integrated in a dual-strained liner of a gate-last process, so as to effectively improve the properties and reliability of the device.


Patent
CAS Institute of Microelectronics | Date: 2016-07-19

A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing alternating insulating and electrode layers on a substrate to form a multi-layer film. The method further includes etching the film to the substrate to form through-holes, each of which defines a channel region. The method further includes depositing barrier, storage, and tunnel layers in sequence on inner walls of through-holes to form gate stacks. The method further includes depositing and incompletely filling a channel material on a surface of the tunnel layer of gate stacks to form a hollow channels. The method further includes forming drains in contact hole regions for bit-line connection in top portions of the hollow channels. The method further includes forming sources in contact regions between the through-holes and the substrate in bottom portions of the hollow channels.


Patent
CAS Institute of Microelectronics | Date: 2015-08-28

There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.


Patent
CAS Institute of Microelectronics | Date: 2016-01-19

An apparatus and a method for epitaxially growing sources and drains of a FinFET device. The apparatus comprises: a primary chamber; a wafer-loading chamber; a transfer chamber provided with a mechanical manipulator for transferring the wafer; an etching chamber for removing a natural oxide layer on the surface of the wafer and provided with a graphite base for positioning the wafer; at least one epitaxial reaction chamber; a gas distribution device for supplying respective gases to the primary chamber, the wafer loading chamber, the transfer chamber, the etching chamber and the epitaxial reaction chamber; and a vacuum device. The wafer loading, transfer, etching, and epitaxial reaction chambers are all positioned within the primary chamber. The apparatus integrates the etching chamber and epitaxial reaction chamber to remove the natural oxide layer on the surface of the wafer in a condition of isolating water and oxygen before the epitaxial reaction has occurred.


Patent
CAS Institute of Microelectronics | Date: 2015-05-29

A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.


A method of depositing a Tungsten (W) layer is provided. The method may include pre-processing a substrate by depositing a SiH_(4) base W film on a surface of the substrate, and depositing a B_(2)H_(6) base W layer on the pro-processed surface. By such a method, it is possible not only to achieve an excellent filling behavior, but also to improve adhesion.


Patent
CAS Institute of Microelectronics | Date: 2015-05-26

An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.


Patent
CAS Institute of Microelectronics | Date: 2015-04-16

A semiconductor device includes: a plurality of fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of fin structures, wherein the gate stack structure includes a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of fin structures and beneath the gate stack structure; and source/drain regions on the plurality of fin structures and at both sides of the gate stack structure along the first direction.

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