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Patent
CAS Institute of Microelectronics | Date: 2014-07-10

A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.


Patent
CAS Institute of Microelectronics | Date: 2014-08-01

A method for manufacturing a FinFET device, including providing a substrate; implementing a source/drain doping on the substrate; etching the doped substrate to form a source region and a drain region; forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel. The fin and the gate are formed after the source/drain doping is implemented on the substrate, so that the source/drain doping is done as a doping for a planar device, which ensures the quality of the source/drain coping and improves the property of the FinFET device.


Patent
CAS Institute of Microelectronics and Jiangnan University | Date: 2016-06-06

A method for preparing a TiAl alloy thin film, wherein a reaction chamber is provided, in which at least one substrate is placed; an aluminum precursor and a titanium precursor are introduced into the reaction chamber, wherein the aluminum precursor has a molecular structure of a structural formula (I); and the aluminum precursor and the titanium precursor are brought into contact with the substrate so that a titanium-aluminum alloy thin film is formed on the surface of the substrate by vapor deposition. The method solves the problem of poor step coverage ability and the problem of incomplete filling with regard to the small-size devices by the conventional methods. Meanwhile, the formation of titanium-aluminum alloy thin films with the aid of plasma is avoided so that the substrate is not damaged by plasma.


Provided are a CMOS device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the CMOS semiconductor device includes an n-type device and a p-type device. The n-type device and the p-type device each may include: a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the n-type device or the p-type device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. For the n-type device, the PTS layer has net negative charges, and for the p-type device, the PTS layer has net positive charges.


Provided are a semiconductor device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the semiconductor device may include a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the semiconductor device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. The semiconductor device may be an n-type device or a p-type device. For the n-type device, the PTS layer may have net negative charges, and for the p-type device, the PTS layer may have net positive charges.


Patent
CAS Institute of Microelectronics | Date: 2016-10-25

A GaN-based enhancement-mode power electronic device and a method for manufacturing the same. The GaN-based enhancement-mode power electronic device comprises: a substrate; a thin barrier Al(In,Ga)N/GaN heterostructure formed on the substrate; a gate, a source, and a drain formed on the thin barrier Al(In,Ga)N/GaN heterostructure. An AlN or SiNx passivation layer is formed on access regions between the gate and the source and between the gate and the drain, respectively, such that two dimensional electron gas is recovered in channels of the thin barrier Al(In,Ga)N/GaN heterostructure below the MN passivation layer by utilizing the MN passivation layer having polarization characteristics, or by using the SiNx passivation layer with positive fixed bulk/interface charges, so as to reduce on-resistance of the device and inhibit high-voltage current collapse in the device.


Patent
CAS Institute of Microelectronics | Date: 2017-02-03

Semiconductor devices and methods for manufacturing the same are provided. An example method may include: forming a sacrificial gate stack on a substrate; forming a gate spacer on sidewalls of the sacrificial gate stack; forming an interlayer dielectric layer on the substrate and planarizing it to expose the sacrificial gate stack; partially etching back the sacrificial gate stack to form an opening; expanding the resultant opening so that the opening is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate; and removing a remaining portion of the sacrificial gate stack and forming a gate stack in a space defined by the gate spacer.


Patent
CAS Institute of Microelectronics | Date: 2014-07-10

A three-dimensional semiconductor device, comprising a plurality of memory cell transistors and a plurality of select transistors at least partially overlapped in the vertical direction, wherein each select transistor comprises a first drain, an active region and a common source formed in the substrate, distributed along the vertical direction, as well as a metal gate distributed around the active region; wherein each memory cell transistor comprises a channel layer distributed perpendicularly to the substrate surface, a plurality of inter-layer insulating layers and a plurality of gate stack structures alternately stacked along the sidewalls of said channel layer, a second drain located on top of said channel layer; wherein said channel layer and said the first drain are electrically connected. In accordance with the three-dimensional semiconductor memory device and manufacturing method of the present invention, the multi-gate MOSFET is formed beneath the stack structure of the memory cell string including vertical channel to serve as the select transistor, this can improve the control characteristics of the gate threshold voltage, reduce the off-state leakage current, prevent the substrate from over-etching, and effectively improve the reliability of the device.


Patent
CAS Institute of Microelectronics | Date: 2016-01-19

An apparatus and a method for epitaxially growing sources and drains of a FinFET device. The apparatus comprises: a primary chamber; a wafer-loading chamber; a transfer chamber provided with a mechanical manipulator for transferring the wafer; an etching chamber for removing a natural oxide layer on the surface of the wafer and provided with a graphite base for positioning the wafer; at least one epitaxial reaction chamber; a gas distribution device for supplying respective gases to the primary chamber, the wafer loading chamber, the transfer chamber, the etching chamber and the epitaxial reaction chamber; and a vacuum device. The wafer loading, transfer, etching, and epitaxial reaction chambers are all positioned within the primary chamber. The apparatus integrates the etching chamber and epitaxial reaction chamber to remove the natural oxide layer on the surface of the wafer in a condition of isolating water and oxygen before the epitaxial reaction has occurred.


A method of depositing a Tungsten (W) layer is provided. The method may include pre-processing a substrate by depositing a SiH_(4) base W film on a surface of the substrate, and depositing a B_(2)H_(6) base W layer on the pro-processed surface. By such a method, it is possible not only to achieve an excellent filling behavior, but also to improve adhesion.

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