Denmark
Denmark

Time filter

Source Type

Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-06-2015 | Award Amount: 23.11M | Year: 2016

The objective of the 3DAM project is to develop a new generation of metrology and characterization tools and methodologies enabling the development of the next semiconductor technology nodes. As nano-electronics technology is moving beyond the boundaries of (strained) silicon in planar or finFETs, new 3D device architectures and new materials bring major metrology and characterization challenges which cannot be met by pushing the present techniques to their limits. 3DAM will be a path-finding project which supports and complements several existing and future ECSEL pilot-line projects and is linked to the MASP area 7.1 (subsection More Moore). Innovative demonstrators and methodologies will be built and evaluated within the themes of metrology and characterization of 3D device architectures and new materials, across the full IC manufacturing cycle from Front to Back-End-Of-Line. 3D structural metrology and defect analysis techniques will be developed and correlated to address challenges around 3D CD, strain and crystal defects at the nm scale. 3D compositional analysis and electrical properties will be investigated with special attention to interfaces, alloys and 2D materials. The project will develop new workflows combining different technologies for more reliable and faster results; fit for use in future semiconductor processes. The consortium includes major European semiconductor equipment companies in the area of metrology and characterization. The link to future needs of the industry, as well as critical evaluation of concepts and demonstrators, is ensured by the participation of IMEC and LETI. The project will directly increase the competitiveness of the strong Europe-based semiconductor Equipment industry. Closely connected European IC manufacturers will benefit by accelerated R&D and process ramp-up. The project will generate technologies essential for future semiconductor processes and for the applications enabled by the new technology nodes.


Grant
Agency: European Commission | Branch: H2020 | Program: IA | Phase: ICT-25-2015 | Award Amount: 3.35M | Year: 2016

Within the food chain of equipment delivery for the semiconductor industry, Europe has kept a very strong position in the metrology area with many companies establishing themselves as main leaders in the field. Hence in line with the objectives of the ICT25 call for innovation action to overcome the (initial) barriers for the successful commercialization of novel European products, this project aims at exploring for a number of metrology solutions their technological readiness, reliability and relevance of the developed protocols, and the COO. The portfolio within the project covers new metrology concepts addressing specifically the processing challenges linked to 3D-Devices and range from probing basic layer properties (composition, electrical properties) in FEOL to control of metallization in BEOL up to issues linked to die stacking. Due to the specific processing steps which need to be addressed, three separate metrology tools will be assessed in this project i.e a Tofsims system (IonTOF) with build-in Scanning Probe stage and FIB column for true 3D-composition profiling, a completely automated micro-Hall and sheet resistance measurement tool (Capres) with additional capabilities for measurements on dedicated test structures (prior to full BEOL) and an GHz acoustic Microscope (Tepla) for probing voids in TSVs and stacked dies. As some of them (IonTOf, Capres) are addressing partly complementary information (composition versus electrical properties), their co-existence in this project creates additional value as beyond the tool assessment also a methodology based on combining these concepts can be explored and certified. Moreover a significant efficiency gain is created as they can employ similar test structures and devices. For each of these tools, the basic metrology concepts are existing and validated in the lab on selected applications but their general applicability field within the semiconductor industry still needs to be established

Loading Capres As collaborators
Loading Capres As collaborators