Canaan Semiconductor Ltd

Shatin, Hong Kong

Canaan Semiconductor Ltd

Shatin, Hong Kong
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Filip V.,University of Bucharest | Filip V.,Zhejiang University | Wong H.,Zhejiang University | Tam W.-S.,Canaan Semiconductor Ltd | Kok C.-W.,Canaan Semiconductor Ltd
2016 5th International Symposium on Next-Generation Electronics, ISNE 2016 | Year: 2016

A simple model of a hetero-structured cathode for electron field emission was developed in order to compare resonant and sequential electron field emission currents. These two components were simultaneously computed through an iterative process. The model assumes that a certain fraction of the batch of electrons that failed to resonantly transit the structure will end up in its quasi-bound states. It was found that, while various slope changes appear in both current-field characteristics, for the sequential tunneling emission, such features are merely interference effects occurring in the potential energy barrier, prior to the electron's transition in the quasi-bound states. Thus, various space charges develop in the structure and reacts back on both the sequential and the resonant parts of the current. © 2016 IEEE.


Tam W.-S.,Canaan Semiconductor Ltd | Kok C.-W.,Canaan Semiconductor Ltd | Lai S.-F.,City University of Hong Kong | Wong H.,City University of Hong Kong
IEEE Region 10 Annual International Conference, Proceedings/TENCON | Year: 2016

A compact model of the loss tangent of the vacuum dielectric capacitor (VDC) in terms of the size of the VDC, capacitance, and ratio of the width of the boundary sealant to the width of the top electrode is presented in this paper. An analytical tool that can determine the optimal size of a VDC to achieve the desired trade-off between the capacitance and loss tangent is described. Although the VDC with a single type of sealant was used as an example to illustrate the idea, the presented methodology is general and can be applied for VDCs constructed with other sealant materials. © 2015 IEEE.


Siu S.-L.,University of Hong Kong | Tam W.-S.,Canaan Semiconductor Ltd | Kok C.-W.,Canaan Semiconductor Ltd | Lai S.-F.,City University of Hong Kong | And 2 more authors.
IEEE Region 10 Annual International Conference, Proceedings/TENCON | Year: 2016

In this paper, the sensitivity distortion of Hall plate based and split-drain magnetic field effect transistor (SSD-MAGFET) based magnetic sensors under the alternating magnetic field is investigated. Based on the outputs of the both hall plate based and SSD-MAGFET based sensors are sinusoidal functions of displacement of a rotating magnetic field strength, we propose to analyze the sensitivity of the sensors by spectral analysis. The empirical results show that conventional Hall plate based sensor suffers from greater spectral distortion when compared to that of SSD-MAGFET based sensors, which implies SSD-MAGFET based sensors can achieve better accuracy in high speed application without the needs of charge accumulation. © 2015 IEEE.


Wong O.-Y.,City University of Hong Kong | Wong H.,City University of Hong Kong | Tam W.-S.,Canaan Semiconductor Ltd | Kok C.-W.,Canaan Semiconductor Ltd
Electronics Letters | Year: 2014

The loss estimation in a switched-capacitor DC-DC converter has caused much controversy because of the uncertainty of the contribution of device parasitics to the power efficiency of a converter. Beginning from a simple equivalent circuit model, a closed-form solution to the maximum achievable power efficiency of a converter in which both the effects of parasitic resistance and capacitance are taken into account is presented. It has been observed that the peak power efficiency of a Dickson charge pump depends mainly on the equivalent parasitic capacitance of a given technology and its operation mode, which is governed by the choices of the coupling capacitance, onresistance of the switch, as well as the operation frequency of the circuit. © The Institution of Engineering and Technology 2014.


Wong O.-Y.,City University of Hong Kong | Wong H.,City University of Hong Kong | Tam W.-S.,Canaan Semiconductor Ltd. | Kok C.-W.,Canaan Semiconductor Ltd.
IEEE Transactions on Power Electronics | Year: 2014

A method that aims at analyzing the dynamic behavior of some two-phase switched-capacitor charge pump circuits is proposed. A recurrence relation on the voltages across the charging capacitors of a given two-phase charge pump circuit is developed. The output voltage and the accumulated charge of a charge pump circuit after any clock cycle were found by solving some basic matrix equations, with a specific loading current and some required initial conditions. The validation of the proposed method was done by SPICE simulations based on a 8 × linear, Fibonacci, and an exponential charge pump. The analysis results were also verified with the simulation results obtained from some charge pump circuits designed with the 0.18 μm CMOS process. Results show that the proposed method can yield a close estimation on the dynamic behavior of a charge pump circuit in most of the designs. We further found that the rising times for the exponential and Fibonacci charge pumps are shorter, especially when the conversion ratio is high, than that of the linear one. © 1986-2012 IEEE.


Wong O.-Y.,City University of Hong Kong | Wong H.,City University of Hong Kong | Tam W.-S.,Canaan Semiconductor Ltd. | Kok C.-W.,Canaan Semiconductor Ltd.
Analog Integrated Circuits and Signal Processing | Year: 2014

This paper aims at investigating some methods for designing an area- and power-efficient Dickson charge pump circuit for on-chip high-voltage source generation. A comprehensive study on two conventional methods, with one of them based on optimizing the number of stage for minimum silicon area (minimum area method) and the other for maximum power efficiency (optimal power method), will be presented by considering both top- and bottom-plate parasitic capacitances. It was found that when the parasitic factors are as large as 0.1, the area and power efficiencies of the charge pumps designed with either the optimal power or minimum area method do not have much degradation. However, when the parasitic factors are small, charge pumps designed with the optimal power and minimum area methods can, respectively, result in a large area and poor power efficiency. The power efficiency of the charge pump designed with the minimum area method may be reduced by 50 %, while the area of the charge pump designed with the optimal power method can be 1-2 times larger, when the parasitic factors are 0.01. Hence, neither the optimal power nor minimum area methods should be used when the parasitic factors are small, unless the power or area is the only concern in the design. With this connection, the number of stage which leads to an area and power-efficient charge pump is suggested. Validity was proved by the good agreement between the simulated and the expected results for some designed charge pump circuits of the proposed design strategy. © 2013 Springer Science+Business Media New York.


Filip L.D.,National Institute of Materials Physics Bucharest | Pintilie L.,National Institute of Materials Physics Bucharest | Tam W.-S.,Canaan Semiconductor Ltd | Kok C.-W.,Canaan Semiconductor Ltd
2016 5th International Symposium on Next-Generation Electronics, ISNE 2016 | Year: 2016

The leakage current for a thin film metal-ferroelectric-metal device was modelled using an electron tunnelling approach. The potential energy through the device was obtained from an electrostatic argument and a balance equation was imposed for the incoming and outgoing currents. Using the obtained leakage current, experimental data was fitted in order to obtain qualitative values for the model parameters. Good agreement between the obtained dielectric constant and numerical calculations performed in the literature. © 2016 IEEE.


Lai S.-F.,City University of Hong Kong | Tam W.-S.,Canaan Semiconductor Ltd | Kok C.-W.,Canaan Semiconductor Ltd | Ng L.-T.,Canaan Semiconductor Ltd | Wong H.,City University of Hong Kong
IEEE Region 10 Annual International Conference, Proceedings/TENCON | Year: 2016

This paper proposes and analyzes a quiescent current control scheme on linear power amplifier, which allows the amplifier to achieve low distortion amplification that is free from zero-crossing distortion as a Class A amplifier, while achieving energy efficiency comparable to a Class B amplifier. The proposed circuit offers great design flexibility by allowing individual adjustment in the quiescent currents flowing in the push/pull output transistors individually. Moreover, the push/pull transistors in the proposed circuit can be implemented in identical NMOS transistors, thus releases the stringent transconductance matching requirement at the output stage. The circuit performance is analytically analyzed and validated by SPICE simulation. © 2015 IEEE.


Wong O.-Y.,City University of Hong Kong | Wong H.,City University of Hong Kong | Tam W.-S.,Canaan Semiconductor Ltd. | Kok C.-W.,Canaan Semiconductor Ltd.
International Journal of Circuit Theory and Applications | Year: 2015

A 4× charge pump using exponential topology is proposed and implemented. Comparing to the conventional implementations, the proposed circuit suppresses the reverse current effectively without using different threshold-voltage transistors and additional capacitors. Also, the body effect found in the charge transfer switches is eliminated. The proposed charge pump is analyzed with the state-space method and fabricated using 0.35 μm complementary metal-oxide-semiconductor process. Results show that the output voltages close to the ideal one, and a maximum power efficiency of 95% was recorded. Copyright © 2013 John Wiley & Sons, Ltd.


Wong O.-Y.,City University of Hong Kong | Wong H.,City University of Hong Kong | Tam W.-S.,Canaan Semiconductor Ltd. | Kok C.-W.,Canaan Semiconductor Ltd.
IET Power Electronics | Year: 2015

The effects of parasitic capacitances on the performances of three common switched-capacitor DC-DC converters operating in the complete charge transfer case were studied with matrix calculation. The study was conducted by describing the top- and bottom-plate parasitic capacitances of a capacitor network in matrix form; these resulted matrices were then employed in some existing solutions so that not only the steady-state performance, but also the dynamic-state performance of a two-phase switched-capacitor DC-DC converter could be evaluated. The proposed method was validated with SPICE simulation and was used to study the final output voltage, start-up time and start-up energy consumption of an exponential, a Fibonacci and a linear converter under different parasitic capacitance effects. © The Institution of Engineering and Technology 2015.

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