Cambridge CMOS Sensors | Date: 2015-02-27
It is disclosed herein a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device is made using partly CMOS or CMOS based processing steps, and it includes a semiconductor substrate, a dielectric region over the semiconductor substrate, a heater within the dielectric region and a patterned layer of noble metal above the dielectric region. The method includes the deposition of a photoresist material over the dielectric region, and patterning the photo-resist material to form a patterned region over the dielectric region. The steps of depositing the photo-resist material and patterning the photo-resist material may be performed in sequence using similar photolithography and etching steps to those used in a CMOS process. The resulting semiconductor device is then subjected to further processing steps which ensure that a dielectric membrane and a metal structure within the membrane are formed in the patterned region over the dielectric region.
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2013.3.1 | Award Amount: 6.22M | Year: 2013
E2SWITCH focuses on Tunnel FET (TFETs) as most promising energy efficient device candidates able to reduce the voltage supply of integrated circuits (ICs) below 0.25V and make them significantly more energy efficient by exploiting strained SiGe/Ge and III-V platforms, with CMOS technological compatibility. A full optimization and DC/AC benchmarking for complementary n- and p-type TFETs, integrated on the same fabrication platform, is proposed. Compact models are developed and implemented in Verilog A, for portability, to support the design of low power ICs with CMOS architectural compatibility for: (i) digital and (ii) analog/RF. The device scalability, operational reliability and the operation from room to high temperature, as required by ITRS metrics, are priorities of our investigations. In order to push even more the III-V and SiGe/Ge TFET performance we propose to study, optimize and experimentally validate new device concepts such as a Density-Of-State (DOS) switch exploiting the effect of dimensionality. The DOS switch will deliver deep subthermal switching (subthreshold swing less than 10mV/decade, for at least four decades of current).An advanced TCAD simulation platform is developed for the selected material systems, able to capture quantum effects and to accurately predict the influence of dimensionality. TCAD will also support the optimization of TFETs on the two proposed material platforms, with emphasis on the role of strain and on the alignment between the tunneling path and the electric field.A full set of characterization techniques including DC, AC, low frequency noise, RF measurements (S-parameters) and large range of temperature is foreseen to support the device optimization, parameter extraction and the calibration of the compact models.We will deliver very first full digital and analog circuit demonstrators and will benchmark their operational performance, reliability and robustness compared to equivalent CMOS technology nodes.
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2011.3.2 | Award Amount: 4.29M | Year: 2011
SOI-HITS is an ambitious, innovative and timely STREP project that will enable significant energy consumption savings and reduce waste in processes such as: combustion in domestic boilers; oil & gas storage and transportation; CO2 capture and sequestration. It aims to deliver at least 15% saving of energy consumption in domestic boiler industry (~40 million domestic boilers in the EU with a growth rate of 15% per year); equating to 3.6 billion Euros saved per year. For this ambitious goal, SOI-HITS will develop innovative CMOS-compatible, Silicon-on-Insulator (SOI) integrated smart microsensor systems, capable of multi-measurand (water vapour, temperature, gas, flow, UV/IR) detection under harsh environment conditions (to 225oC, high water vapour level). SOI technology has several advantages over bulk silicon: enhanced electro-thermal isolation giving lower power consumption, ease of forming arrays of MEMS membranes, option of tungsten as a high temperature CMOS metal, direct integration of high-performance temperature and UV optical solid-state sensors. The smart multisensor chip will comprise multiple micro-hotplates with tungsten micro-heaters onto which selective nanostructured and thin film metal oxide sensing layers have been deposited. For the gas sensors (CO2 (concentration 6-10%, CO (0-1000ppm), and H2S (0-100ppm)), we will achieve fast thermal response time of a few ms and loss per micro-hotplate below 0.2mW/oC. Water vapour sensors, flow sensors (for liquid & gas) and precision on-chip temperature controllers will be also integrated. On-chip processing electronics, including drive circuitry, filters, amplifiers, processing circuits and analogue to digital interfaces, operating at 225oC, will be developed. The extension of the SOI platform to optical detectors, such as UV photodiode flame detectors and IR combined sources/detectors, will be explored. Finally development of a High Temperature SIP (system in a package) will enable real-world demonstrators.
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2013.3.3 | Award Amount: 18.11M | Year: 2013
The concept of the MSP project is based on a multi-project wafer approach that enables the development of highly innovative components and sensors based on Key Enabling Technologies (KETs). The central objective of the MSP-project is the development of a technology and manufacturing platform for the 3D-integration of sophisticated components and sensors with CMOS technology being the sound foundation for cost efficient mass fabrication.\nThe MSP project is focused on the development of essential components and sensors that are required for the realization of miniaturized smart systems capable for indoor and outdoor environmental monitoring:\n\ Gas sensors for detection of potentially harmful or toxic gases\n\ Sensors for particulate matter and ultrafine particles\n\ Development of metamaterial based IR sensors for presence and fire detection\n\ Development of optimized IR detectors based on SOI thermopiles\n\ Development of highly efficient photovoltaics and piezoelectrics for energy harvesting\n\ Development of light sensor and UV-A/B sensors.\nThe rigorous employment of Through-Silicon-Via technology enables a highly flexible plug-and play 3D-integration of these components and sensors to miniaturized smart systems with significantly advanced functionalities. The goal of the MSP project is the development of a smart multi-sensor platform for distributed sensor networks in Smart Building Management, which are able to communicate with smart phones.\nThe MSP project covers the heterogeneous integration of KETs and contributes to reinforce European industrial leadership through miniaturization, performance increase and manufacturability of innovative smart systems. The MSP project is focused on emerging innovative technologies and processes for customer needs with a special emphasis on SMEs to enable their take up of KETs for competitive, highly performing product development.
Agency: Cordis | Branch: H2020 | Program: RIA | Phase: ICT-25-2015 | Award Amount: 2.19M | Year: 2016
Nanonets2Sense proposes a new technological approach, where random networks of nanowires, called nanonets (NN), allow biosensors for medical applications to be integrated at low cost with a 3D integration scheme. The final objective of the project is to demonstrate 3D above-IC integration of nanonet-based sensing devices on a CMOS platform. By using nanonets as sensing material, our synergetic approach retains the advantages of nanowires (NW) properties without the associated technological burden. With a smart combination of bottom-up and top-down technologies and a low processing temperature (<400C) compatible with CMOS integration, it allows 3D integration into a compact sensor, where the sensing element, which is exposed to breath or biofluids, is integrated above the CMOS detection circuit, which is naturally protected. Nanonets2Sense will address all material, device and circuit issues. It will develop the integration process that allows the 3D above-IC integration of NN-based sensing devices on a CMOS platform, optimize sensor performance by engineering nanonet properties and device dimensions, analyse NN-based devices operation and performance and optimize readout accordingly, demonstrate the viability of the integration approach by fabricating a proof-of-concept integrated sensor that realizes 3D SoC integration of a NN-based sensing device with its CMOS read-out. Nanonets2Sense is thus providing a new technological building block to enhance CMOS chip functionality with biosensing capability. It combines high performance at low cost and the impact is enhanced by the fact that the approach is generic and can be adapted to a large variety of NW and target molecules. Nanonets2Sense relies on well recognized European partners, including academic, SME and large company, which represent the whole chain from basic and applied research to foundry and products development, ensuring that exploitation will combine sounded physical concepts with industrial vision.
Agency: Cordis | Branch: FP7 | Program: CP-IP | Phase: FoF.NMP.2011-6 | Award Amount: 10.54M | Year: 2011
Graphene has some unique properties resulting from its linear dispersion band structure, its high carrier mobility, and its low dimensionality. However, its use is presently limited by its synthesis and mass production. The project aims to develop the first roll-based chemical vapour deposition (CVD) machine for the mass production of few-layer graphene for transparent electrodes for LED and display applications, and adapts the process conditions of a wafer-scale carbon nanotube growth system to provide a low-cost batch process for graphene growth on silicon. The project focuses on applications such as transparent electrodes for OLEDs and GaN LEDs, optical switches, plasmonic waveguides, VLSI interconnects, sensors and RF NEMs.
Agency: Cordis | Branch: FP7 | Program: CP-IP | Phase: NMP-2008-4.0-3 | Award Amount: 8.35M | Year: 2009
Carbon nanotubes are materials with a set of unique electrical, mechanical, surface and thermal properties. Yet their adoption in mainstream applications has been limited by mass production and device integration. This project develops the first 300mm wafer-scale equipment for production of carbon nanotubes on surfaces. The project will cover the design, engineering, process control, quality assurance, qualification and process development. It will develop applications in cathodes for time resolved X-ray sources for X-ray tomography, cathodes for high power microwave amplifiers, interconnects for VLSI, thermal management surfaces, low stiction surfaces for micro-fluidic channels and filters, wafer scale fabrication of spin valve devices, and sensor surfaces for integrated sensors on CMOS.
Cambridge CMOS Sensors | Date: 2014-06-10
An infra-red (IR) device comprising a dielectric membrane formed on a silicon substrate comprising an etched portion; and at least one patterned layer formed within or on the dielectric membrane for controlling IR emission or IR absorption of the IR device, wherein the at least one patterned layer comprises laterally spaced structures.
Agency: GTR | Branch: Innovate UK | Program: | Phase: Smart - Development of Prototype | Award Amount: 111.56K | Year: 2014
Cambridge CMOS Sensors (CCS) is one of the leading providers of ultra-low power, high temperature micro-hotplate devices that is readily integrated on the same silicon platform used for microprocessor chips, thereby enabling the capabilities of producing a new generation miniature sensors for medical, consumer, industrial and automotive applications. In collaboration with University of Cambridge, and large multi-national silicon foundry partners, CCS has pioneered the production of these micro-hotplates by developing and optimising Deep Reactive Ion Etching (DRIE) process that is used for making Micro Electromechanical System (MEMS) components. The benefit of CCS technology is that it uses standard Complementary Metal Oxide Semiconductor (CMOS), silicon wafers, which is ideal for high volume, low cost applications. These micro-hotplate devices have many uses, which includes miniature catalytic and resistive gas sensors, broadband mid-infrared emitter for gas sensing and spectroscopy applications, flow sensors, and smart sensors with on-chip control circuits. One of the first products developed by CCS based on micro-hotplates is the broadband midinfrared emitter. These emitters are being used for Non-Dispersive Infrared (NDIR) gas sensing applications for greenhouse gas monitoring (such as carbon dioxide, methane, nitrogen oxide) as well as human breath analysis for medical applications (such as carbon dioxide monitoring). Furthermore, using the same platform technology CCS has also developed highly innovative matching broadband IR detectors that are used with the emitter for NDIR gas sensing application. In this project we aim to take advantage of the above unique technological advantages to develop one of the most compact carbon dioxide, (CO2) gas sensors for human breath analysis that will focus on enabling low cost capnography applications but without compromising on accuracy.
Cambridge CMOS Sensors | Date: 2012-05-08
An IR source in the form of a micro-hotplate device including a CMOS metal layer made of at least one layer of embedded on a dielectric membrane supported by a silicon substrate. The device is formed in a CMOS process followed by a back etching step. The IR source also can be in the form of an array of small membranesclosely packed as a result of the use of the deep reactive ion etching technique and having better mechanical stability due to the small size of each membrane while maintaining the same total IR emission level. SOI technology can be used to allow high ambient temperature and allow the integration of a temperature sensor, preferably in the form of a diode or a bipolar transistor right below the IR source.