Greater Noida, India
Greater Noida, India

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Patent
Imec and Cadence Design Systems Inc. | Date: 2014-03-19

A method is provided to test a modular integrated circuit (IC) 100 comprising: testing a module-under-test (MUT) 101B within the IC 100 while causing a controlled toggle rate within a first neighbor module 101A of the MUT 101B; wherein the controlled toggle rate within the first neighbor module 101A is selected so that toggling within the first neighbor module 101A has substantially the same effect upon operation of the MUT 101B as operation of the first neighbor module 101A would have during actual normal functional operation of the first neighbor module 101A.


Grant
Agency: GTR | Branch: EPSRC | Program: | Phase: Research Grant | Award Amount: 298.00K | Year: 2016

Nanosystems are promising high performance alternatives to existing sensing and processing systems. However, their cost is often enhanced by object-oriented design and manufacturing, wherein a costly nanomanufacturing process is used for making one product for one application. By using structured design philosophies similar to the ones used in popular Complementary mental oxide semiconductor (CMOS) Integrated Circuits, we propose to showcase the feasibility of cheap nanosensors as well as integration of nanosystems with existing manufacturing facilities. This provides an opportunity for existing IC design houses to include nanosystems in their design flow, while developing a novel single chip low cost multifunctional nano-sensor array made from Graphene.


Patent
Cadence Design Systems Inc. | Date: 2015-06-15

Electronic design automation systems and methods for extracting Microelectromechanical systems (MEMS) objects from a manufacturing MEMS layout are described for MEMS layouts directed to MEMS devices including mass and spring objects. Pattern recognition is used on a MEMS layer of the MEMS layout to identify beams and supports. The identified beams and supports are then used to derive a set of intermediate MEMS objects. The intermediate MEMS objects are used to derive a set of output objects, where the set of output objects includes at least two mass objects and at least one active spring object. The set of output objects may then be used to generate a Lagrangian model of the MEMS device described by the MEMS layout.


Patent
Cadence Design Systems Inc. | Date: 2013-03-12

A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.


A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-tos denoting start and end points for each route by invoking a star_route command in a router that implements interconnections as specified. Routing results are validated by checking for routing violations, including shared segments and width violations. Violations are marked for correction.


Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes.


Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.


Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.


Patent
Cadence Design Systems Inc. | Date: 2014-03-05

Technology for finite-state machine (FSM) encoding during design synthesis for a circuit is disclosed. The encoding of the FSM may include determining values of a multi-bit state register that are to represent particular states of the FSM. These values may be determined based on possible states of the FSM, possible transitions between the states, probabilities of particular transitions occurring, amounts of false switching associated with particular transitions, area estimates for logic respectively associated with states of the FSM, and/or the like. The values may also be determined based on power considerations, such as estimated power consumption for the circuit. The design synthesis may include generation of a structural description of the encoded FSM.


Patent
Cadence Design Systems Inc. | Date: 2014-03-07

Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuits behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements.

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