Saint-Rémy-de-Provence, France
Saint-Rémy-de-Provence, France

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Method for assisting the movement of an agent in an interior environment. Method allowing the calculation of an itinerary on a dynamics graph. The dynamics graph is produced by those circulating in the zone to be mapped, the paths travelled being recorded by means of a geopositioning system compatible with inside use. The zone to be mapped is modelled in elementary volumes recoded in a zone database. The recorded paths are used to create a graph whereon an itinerary is calculated between two points, each of which being associated with an elementary volume of the zone.


Patent
Bull SAS | Date: 2017-04-19

The invention relates to a device for searching for element correspondence in a list, said device comprising: a plurality of content-adressable memory modules configured so as to be able to compare in parallel an input element with the content thereof, the list being represented by the concatenation of the valid content of said memories in an order defined by a list of priority, a module for the determination, in said list of priority, of the first module wherein the input element corresponds to an element stored in said module, and a module for reading the first element of said determined module corresponding to the input element.


Grant
Agency: European Commission | Branch: H2020 | Program: IA | Phase: FoF-09-2015 | Award Amount: 11.42M | Year: 2015

Fortissimo 2 will drive the uptake of advanced modelling, simulation and data analytics by European engineering and manufacturing SMEs and mid-caps. Such an uptake will deliver improved design processes, better products and services, and improved competitiveness. For the European Union as a whole this means improved employment opportunities and economic growth. The importance of advanced ICT to the competitiveness of both large and small companies in the engineering and manufacturing domain is well established. Despite early successes in this area, there are still many barriers to the uptake of such solutions, not least of which are the initial cost and complexity of adoption, particularly in the context of challenging trading conditions. This proposal targets the ICT Innovation for Manufacturing SMEs (I4MS) action line (Phase 2) and builds on Phase 1 of that initiative. Phase 2 addresses the adoption of next generation ICT advances in the manufacturing domain. At the core of Fortissimo 2 are three tranches of Application Experiments (~35 in total). An initial set is included in this proposal and two further sets will be obtained through Open Calls for proposals. These experiments will be driven by the requirements of first-time users (predominately SMEs) and will bring together actors from across the value chain, from cycle providers to domain experts via the Fortissimo Marketplace. This will enable innovative solutions to manufacturing challenges, leading to new and improved design processes, products and services. A key feature of Fortissimo 2 will be the adaption of the Marketplace to meet the needs of end-users. It will offer a responsive and reliable service to companies which want to access HPC and Big resources and expertise. Fortissimo 2 initially involves 732 months of effort, a total cost of 11.1m and EC funding of 10m over a duration of three years, commensurate with achieving its ambitious goals.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: FETHPC-1-2014 | Award Amount: 8.63M | Year: 2015

ExaNoDe will investigate, develop and pilot (technology readiness level 7) a highly efficient, highly integrated, multi-way, high-performance, heterogeneous compute element aimed towards exascale computing and demonstrated using hardware-emulated interconnect. It will build on multiple European initiatives for scalable computing, utilizing low-power processors and advanced nanotechnologies. ExaNoDe will draw heavily on the Unimem memory and system design paradigm defined within the EUROSERVER FP7 project, providing low-latency, high-bandwidth and resilient memory access, scalable to Exabyte levels. The ExaNoDe compute element aims towards exascale compute goals through: Integration of the most advanced low-power processors and accelerators across scalar, SIMD, GPGPU and FPGA processing elements supported by research and innovation in the deployment of associated nanotechnologies and in the mechanical requirements to enable the development of a high-density, high-performance integrated compute element with advanced thermal characteristics and connectivity to the next generation of system interconnect and storage; Undertaking essential research to ensure the ExaNoDe compute element provides necessary support of HPC applications including I/O and storage virtualization techniques, operating system and semantically aware runtime capabilities and PGAS, OpenMP and MPI paradigms; The development of an instantiation of a hardware emulation of interconnect to enable the evaluation of Unimem for the deployment of multiple compute elements and the evaluation, tuning and analysis of HPC mini-apps. Each aspect of ExaNoDE is aligned with the goals of the ETP4HPC. The work will be steered by first-hand experience and analysis of high-performance applications, their requirements and the tuning of their kernels.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: FETHPC-1-2014 | Award Amount: 7.97M | Year: 2015

The main target of the Mont-Blanc 3 project European Scalable and power efficient HPC platform based on low-power embedded technology is the creation of a new high-end HPC platform (SoC and node) that is able to deliver a new level of performance / energy ratio whilst executing real applications. The technical objectives are: 1. To design a well-balanced architecture and to deliver the design for an ARM based SoC or SoP (System on Package) capable of providing pre-exascale performance when implemented in the time frame of 2019-2020. The predicted performance target must be measured using real HPC applications. 2. To maximise the benefit for HPC applications with new high-performance ARM processors and throughput-oriented compute accelerators designed to work together within the well-balanced architecture. 3. To develop the necessary software ecosystem for the future SoC. This additional objective is important to maximize the impact of the project and make sure that this ARM architecture path will be successful in the market. The project shall build upon the previous Mont-Blanc & Mont-Blanc 2 FP7 projects, with ARM, BSC & Bull being involved in Mont-Blanc 1, 2 and 3 projects. It will adopt a co-design approach to make sure that the hardware and system innovations are readily translated into benefits for HPC applications. This approach shall integrate architecture work (WP3 & 4 - on balanced architecture and computing efficiency) together with a simulation work (to feed and validate the architecture studies ) and work on the needed software ecosystem.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-04-2015 | Award Amount: 3.20M | Year: 2016

Computer systems have faced significant power challenges over the past 20 years; these challenges have shifted from the devices and circuits level, to their current position as first-order constraints for system architects and software developers. TANGOs goal is to characterise factors which affect power consumption in software development and operation for heterogeneous parallel hardware environments. Our main contribution is the combination of requirements engineering and design modelling for self-adaptive software systems, with power consumption awareness in relation to these environments. The energy efficiency and application quality factors are integrated in the application lifecycle (design, implementation, operation). To support this, the key novelty of the project is a reference architecture and its implementation. Moreover, a programming model with built-in support for various hardware architectures including heterogeneous clusters, heterogeneous chips and programmable logic devices will be provided. TANGO will create a new cross-layer programming approach for heterogeneous parallel hardware architectures featuring automatic code generation including software and hardware modelling. This will consider power, performance, data location and time criticality optimization, in addition to security and dependability on the target hardware architecture. These results will be demonstrated in two real-world applications: reconfigurable power optimized connected platform and HPC. In order to improve collaboration and sustainability of TANGOs and fellow projects results, TANGO considers the foundation of a Research Alliance in which complementary research efforts into novel programming approaches will nucleate, leading to a strong research collaboration and effective integration of project results.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: EINFRA-5-2015 | Award Amount: 4.94M | Year: 2016

This Centre of Excellence will advance the role of computationally based modelling and simulation within biomedicine. Three related user communities lie at the heart of the CoE: academic, industrial and clinical researchers who all wish to build, develop and extend such capabilities in line with the increasing power of high performance computers. Three distinct exemplar research areas will be pursued: cardiovascular, molecularly-based and neuro-musculoskeletal medicine. Predictive computational biomedicine involves applications that are comprised of multiple components, arranged as far as possible into automated workflows in which data is taken, from an individual patient, processed, and combined into a model which produces predicted health outcomes. Many of the models are multiscale, requiring the coupling of two or more high performance codes. Computational biomedicine holds out the prospect of predicting the effect of personalised medical treatments and interventions ahead of carrying them out, with all the ensuing benefits. Indeed, in some cases, it is already doing so today. The CoE presents a powerful consortium of partners and has an outward facing nature and will actively train, disseminate and engage with these user communities across Europe and beyond. Because this field is new and growing rapidly, it offers numerous innovative opportunities. There are three SMEs and three enterprises within the project, as well as eight associate partners drawn from across the biomedical sector, who are fully aware of the vast potential of HPC in this domain. We shall work with them to advance the exploitation of HPC and will engage closely with medical professionals through our partner hospitals in order to establish modeling and simulation as an integral part of clinical decision making. Our CoE is thus user-driven, integrated, multidisciplinary, and distributed; presenting a vision that is in line with the Work Programme.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: FETHPC-1-2014 | Award Amount: 7.88M | Year: 2015

Worldwide data volumes are exploding and islands of storage remote from compute will not scale. We will demonstrate the first instance of intelligent data storage, uniting data processing and storage as two sides of the same rich computational model. This will enable sophisticated, intention-aware data processing to be integrated within a storage systems infrastructure, combined with the potential for Exabyte scale deployment in future generations of extreme scale HPC systems. Enabling only the salient data to flow in and out of compute nodes, from a sea of devices spanning next generation solid state to low performance disc we enable a vision of a new model of highly efficient and effective HPC and Big Data demonstrated through the SAGE project. Objectives - Provide a next-generation multi-tiered object-based data storage system (hardware and enabling software) supporting future-generation multi-tier persistent storage media supporting integral computational capability, within a hierarchy. - Significantly improve overall scientific output through advancements in systemic data access performance and drastically reduced data movements. - Provides a roadmap of technologies supporting data access for both Exascale/Exabyte and High Performance Data Analytics. - Provide programming models, access methods and support tools validating their usability, including Big-Data access and analysis methods - Co-Designing and validating on a smaller representative system with earth sciences, meteorology, clean energy, and physics communities - Projecting suitability for extreme scaling through simulation based on evaluation results. Call Alignment: We address storage data access with optimised systems for converged Big Data and HPC use, in a co-design process with scientific partners and applications from many domains. System effectiveness and power efficiency are dramatically improved through minimized data transfer, with extreme scaling and resilience.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-04-2015 | Award Amount: 6.28M | Year: 2016

VINEYARD will develop an integrated platform for energy-efficient data centres based on new servers with novel, coarse-grain and fine-grain, programmable hardware accelerators. It will, also, build a high-level programming framework for allowing end-users to seamlessly utilize these accelerators in heterogeneous computing systems by using typical data-centre programming frameworks (e.g. MapReduce, Storm, Spark, etc.). VINEYARD will develop two types of energy-efficient servers integrating two novel hardware accelerator types: coarse-grain programmable dataflow engines and fine-grain all-programmable FPGAs that accommodate multiple ARM cores. The former will be suitable for data centre applications that can be represented in dataflow graphs while the latter will be used for accelerating applications that need tight communication between the processor and the hardware accelerators. Both types of programmable accelerators will be customized based on application requirements, resulting in higher performance and significantly reduced energy budgets. VINEYARD will additionally develop a new programming framework and the required system software to hide the programming complexity of the resulting heterogeneous system based on the hardware accelerators. This programming framework will also allow the hardware accelerators to be swapped in and out of the heterogeneous infrastructure so as to offer efficient energy use. VINEYARD will foster the expansion of the soft-IP cores industry, currently limited in the embedded systems, to in data centre market. The VINEYARD consortium has strong industrial foundations, and covers the whole value chain in the data-centre ecosystem; from the data-centre vendors up to the data-centre application programmers. VINEYARD plans to demonstrate the advantages of its approach in three real use-cases a) a bioinformatics application for high-accuracy brain modelling, b) two critical financial applications and c) a big-data analysis application.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-06-2016 | Award Amount: 4.83M | Year: 2016

The project aims at producing a European Cloud Database Appliance for providing a Database as a Service able to match the predictable performance, robustness and trustworthiness of on premise architectures such as those based on mainframes. The project will evolve cloud architectures to enable the increase of the uptake of cloud technology by providing the robustness, trustworthiness, and performance required for applications currently considered too critical to be deployed on existing clouds. CloudDBAppliance will deliver a cloud database appliance featuring: 1. A scalable operational database able to process high update workloads such as the ones processed by banks or telcos, combined with a fast analytical engine able to answer analytical queries in an online manner. 2. A Hadoop data lake integrated with the operational database to cover the needs from companies on big data. 3. A cloud hardware appliance leveraging the next generation of hardware to be produced by Bull, the main European hardware provider. This hardware is a scale-up hardware similar to the one of mainframes but with a more modern architecture. Both the operational database and the in-memory analytics engine will be optimized to fully exploit this hardware and deliver predictable performance. Additionally, CloudDBAppliance will deal with the need to tolerate catastrophic cloud data centres failures (e.g. a fire or natural disaster) providing data redundancy across cloud data centres.

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