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Papa D.A.,Broadway Technology | Markov I.L.,University of Michigan
Lecture Notes in Electrical Engineering | Year: 2013

Physical synthesis tools are responsible for achieving timing closure. Starting with 130 nm designs, multiple cycles are required to cross the chip, making latch placement critical to success. We present a new physical synthesis optimization for latch placement called Rip up and move boxes with linear evaluation (RUMBLE) that uses a linear timing model to optimize timing by simultaneously re-placing multiple gates. RUMBLE runs incrementally and in conjunction with static timing analysis to improve the timing for critical paths that have already been optimized by placement, gate sizing, and buffering. © 2013 Springer Science+Business Media New York. Source


Papa D.A.,Broadway Technology | Markov I.L.,University of Michigan
Lecture Notes in Electrical Engineering | Year: 2013

A fundamental challenge addressed by physical synthesis is reducing circuit delay by altering timing-critical paths. Several techniques can be applied to achieve this optimization: buffer insertion, gate sizing, cell movement, etc. In this work, we propose a powerful new technique that moves and resizes multiple cells simultaneously to straighten critical paths, thereby reducing delay and improving worst negative slack. © 2013 Springer Science+Business Media New York. Source


Papa D.A.,Broadway Technology | Markov I.L.,University of Michigan
Lecture Notes in Electrical Engineering | Year: 2013

Techniques covered in previous chapters have been developed primarily to operate in limited optimization windows, ranging from several gates to functional units of a CPU. © 2013 Springer Science+Business Media New York. Source


Papa D.A.,Broadway Technology | Markov I.L.,University of Michigan
Lecture Notes in Electrical Engineering | Year: 2013

The impact of physical synthesis on design performance is increasing as process technology scales. Current physical synthesis flows generally perform a series of individual netlist transformations based on local timing conditions. However, such optimizations lack sufficient perspective or scope to achieve timing closure in many cases. To address these issues, we develop an integrated transformation system that performs multiple optimizations simultaneously on larger design partitions than existing approaches. Our system, SPIRE, combines physically-aware register retiming, along with a novel form of logic cloning and register placement. SPIRE also incorporates a placement-dependent static timing analyzer (STA) with a delay model that accounts for buffering and is suitable for physical synthesis. © 2013 Springer Science+Business Media New York. Source


Papa D.A.,Broadway Technology | Markov I.L.,University of Michigan
Lecture Notes in Electrical Engineering | Year: 2013

Sophisticated integrated circuits (ICs) can be classified as processors (CPUs), application-specific integrated circuits (ASICs) or systems-on-a-chip (SoCs), which embed CPUs and intellectual property blocks into ASICs. Mass-produced on silicon chips, these circuits fuel consumer and industrial electronics, maintain national and international computer networks, coordinate transportation and power grids, and ensure the competitiveness of military systems. The design of new integrated circuits requires sophisticated optimization algorithms, software and methodologiescollectively called Electronic Design Automation (EDA)which leverage synergies between Computer Science, Computer Engineering and Electrical Engineering. © 2013 Springer Science+Business Media New York. Source

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